Z86E0412PSC1860 ZILOG [Zilog, Inc.], Z86E0412PSC1860 Datasheet
Z86E0412PSC1860
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Z86E0412PSC1860 Summary of contents
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Z86E02/E04/E08/E09 SL1995 Z8 CMOS OTP Microcontrollers Programming Specification PS009201-0301 ZiLOG Worldwide Headquarters • 910 E. Hamilton Avenue • Campbell, CA 95008 Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com ...
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This publication is subject to replacement by a later edition. To determine whether a later edition exists request copies of publications, contact: ZiLOG Worldwide Headquarters 910 E. Hamilton Avenue Campbell, CA 95008 Telephone: 408.558.8500 Fax: 408.558.8300 www.ZiLOG.com Windows ...
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Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1. Top-Level Programming Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Figure 2. 18-Pin DIP/SOIC Pin ...
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List of Tables Table 1. Output Parallel Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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General Description The EPROM Programming interface is a byte-wide data interface with 7 control inputs and a 17-wire connection. This document describes the EPROM interface pertinent to the following parts: Z86E02 SL1995 Z86E04 SL1995 Z86E08 SL1995 Z86E09 SL1995 Top-Level Programming ...
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Figure 1. Top-Level Programming Sequence Next Address PS009201-0301 Z86E02/E04/E08/E09 SL1995 Z8 CMOS OTP Microcontrollers Start Power-On Reset Send Unlock and Mode Codes Program Data at Set Address Verify Data at Set Address Pass Overprogram at Set Address ...
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Parallel Programming Interface The EPROM interface is a 17-wire connection. Review the part-specific pin dia- grams in Figures 2 through 5 for part pin-out. Pin Diagrams Device pin-out diagrams for the 18-pin DIP/SOIC and 20-pin SSOP are shown in Figures ...
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Figure 4. 20-Pin SSOP Pin Configuration, STANDARD Mode P24 1 P25 2 P26 3 P27 OUT P31 P32 10 Figure 5. 20-Pin SSOP Pin Configuration, EPROM Mode ...
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OTP Memory Size The device is offered in 4 memory configurations. Table 3 lists the available sizes of EPROM memory. Table 3. EPROM Size Devices Memory Size Z86E02 Z86E04 Z86E08 Z86E09 Device Operation The device must first be unlocked before ...
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Apply one clock pulse Force the Port 2 pins with F0h . 10. Apply one clock pulse to X 11. Force the Port 2 pins with 0Fh . 12. Apply one clock pulse to X 13. ...
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Figure 6. Unlock Sequence IRESET CLEAR EPM (CE CLOCK ...
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Table 4. Unlock Sequence Conditions EPROM Signal D0–D3 D4–D7 GND OUT OE EPM V PP CLEAR CLOCK PGM Table 5. Power-On Reset Pin Conditions EPROM Signal D0–D3 D4–D7 GND V CC ...
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EPROM Modes The device offers two modes of operation. Table 6 lists the available mode options. Table 6. Mode Selections Value Description A EPROM Array Read and Write modes B Option Bit Program and Verify modes Top Level Operations Figure ...
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EPROM Array Modes EPROM ARRAY READ/WRITE Mode Entry 1. To enter EPROM ARRAY READ/WRITE mode, all pins must be set as per Table 7. 2. EPM is lowered lowered The V is ...
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Figure 8. EPROM ARRAY READ/WRITE Mode Entry Functional Timing CLEAR EPM CLOCK ...
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Table 7. EPROM ARRAY READ/WRITE Mode Entry Conditions (Continued) EPROM Signal CLEAR CLOCK PGM EPROM ARRAY READ Mode Operation 1. Perform Steps 1 through 6 of the EPROM ARRAY READ/WRITE mode entry (see the EPROM ARRAY READ/WRITE Mode Entry operation, ...
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Figure 9. EPROM ARRAY READ Mode Functional Timing CLEAR EPM CLOCK ...
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Table 8. EPROM ARRAY READ Mode Conditions (Continued) CLEAR CLOCK PGM EPROM ARRAY PROGRAM AND VERIFY Mode Operation 1. Perform the EPROM ARRAY READ/WRITE mode entry (see the ARRAY READ/WRITE Mode Entry to Step 2. 2. Reset the address counter ...
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Repeat Steps until the last address is read. 15. Because the address is sequentially accessed, a previously-accessed address can only be programmed or read by resetting the address counter to 0000h and clocking the address counter ...
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Table 9. EPROM ARRAY PROGRAM AND VERIFY Mode Conditions (Continued EPM V PP CLEAR CLOCK PGM Option Bit Modes Table 10 lists the device’s available option bits and their default states. Table 10. Option Bit Values* Bit Option ...
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After a delay of at least 1µs minimum from V 7. The CLOCK is raised pulsed Low The CLOCK is lowered to V 10. Repeat steps six more ...
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Table 11. OPTION BIT PROGRAM AND VERIFY Mode Entry Conditions (Continued EPM V PP CLEAR CLOCK PGM OPTION BIT PROGRAM AND VERIFY Mode Operation 1. Perform the Option Bit READ/WRITE Mode Entry operation (see PROGRAM AND VERIFY ...
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If the address location is not programmed after the 25th try, then the device is failed. 10. If the address location shows that it is programmed, then the address location is then overprogrammed with three times the total accumulated ...
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Table 12. OPTION BIT PROGRAM AND VERIFY Mode Conditions (Continued) OE EPM V PP CLEAR CLOCK PGM OPTION BIT READ Mode Operation 1. Perform the Option Bit READ/WRITE Mode Entry operation (see PROGRAM AND VERIFY Mode Entry 2. CLOCK is ...
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Figure 13. OPTION BIT READ Mode Functional Timing CLEAR EPM CLOCK ...
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Figure 14. Power-Down Functional Timing CLEAR 0V EPM V (CE CLOCK PGM 0V Data Not connected (Port ...
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EPROM I/O Timing The following section details the programming and verification of the OTP. Input and output timing is illustrated in Figure 15. Timing specifications are provided in Table 14. Voltage specifications are provided in Table 15. Figure 15. Z86E0x ...
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Table 14. Timing Specifications (Continued) Parameters Name 8 Data hold time 9 OE setup time 10 Data access time 11 OE width 12 Data output float time Table 15. Voltage Specifications Symbol Description V Programming supply voltage PROG I Programming ...
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Figure 16. Z86E0x Additional Timing Waveform CLOCK T9 T12 CLEAR OE T7 Address 0010h T13 Data Valid Table 16. Z86E0x Additional Timing Specifications Parameter Name T1 CLEAR Width T2 Input CLOCK High T3 Input CLOCK Period T4 Input CLOCK Low ...
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Table 16. Z86E0x Additional Timing Specifications (Continued) Parameter Name T11 CLEAR to Address Counter Out Delay T12 CLOCK Rising to OE Falling T13 Data Access Time Programming Flow Figures 17 and 18 illustrate the flow of the EPROM ARRAY PROGRAM, ...
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Figure 17. EPROM ARRAY PROGRAM, VERIFY, and READ Algorithm PS009201-0301 Z8 CMOS OTP Microcontrollers Start Power-On Reset V = 5.0V CC Send Unlock Sequence and Mode A Select Clear Address Counter to First Location Program 1 ms ...
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Figure 18. EPROM ARRAY READ Algorithm PS009201-0301 Start Power-On Reset V = 5.0V CC Send Unlock Sequence and Mode A Select Clear Address Counter to First Location EPROM Verify One Byte Pass No Increment Address Final Address? Yes Device Passed ...
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Figure 19. OPTION BIT PROGRAM, VERIFY, and READ Algorithm Note: *It is assumed that the user has already selected the option bits prior to this step. PS009201-0301 Z86E02/E04/E08/E09 SL1995 Z8 CMOS OTP Microcontrollers Start Power-On Reset V = 5.0V CC ...
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Figure 20. OPTION BIT READ Algorithm Note: *It is assumed that the user has already selected the option bits prior to this step. PS009201-0301 Z86E02/E04/E08/E09 SL1995 Z8 CMOS OTP Microcontrollers Start Power-On Reset V = 5.0V CC Send Unlock Sequence ...
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Recommendations to Third-Party Programmers ZiLOG recommends the top-level flow illustrated in Figure 21 for programming user code and option bits into OTP. Figure 21. Third-Party Top-Level Algorithm ZiLOG recommends that third-party programmers offer the following features for OTP operations. • ...
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Checksum of buffer/RAM • Program option bits as a sole option • Read option bits as a sole option Precharacterization Product The product represented by this document is newly introduced and ZiLOG has not completed the full characterization of ...
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Third Party Developer Feedback Form The Z86E02/E04/E08/E09 SL1995 Programming Specification If you experience any problems while operating this product you note any inaccuracies while reading this Product Specification, please copy and complete this form, then mail or fax ...