Z86E0412PSC1860 ZILOG [Zilog, Inc.], Z86E0412PSC1860 Datasheet - Page 10

• Manufacturer Part Number: Z86E0412PSC1860
• Description: Z8 CMOS OTP Microcontrollers
• Manufacturer: ZILOG [Zilog, Inc.]

Device Operation
PS009201-0301
OTP Memory Size
Unlock Sequence into EPROM Mode
Note:
The device is offered in 4 memory configurations. Table 3 lists the available sizes
of EPROM memory.
Table 3. EPROM Size
The device must first be unlocked before it can enter EPROM mode. Otherwise,
the device remains in STANDARD mode. The device cannot be programmed in
STANDARD mode. It can only be programmed in EPROM mode. The following
sequence details the unlock procedure.
The following unlock sequence is valid for all parts.
1. A POR must be completed before unlock operations begin. The X
2. Any time after POR, when the internal signal IRESET is Low. The unlock
3. While the X
4. Apply one clock pulse to X
5. Force the Port 2 pins with 5Ah .
6. Apply one clock pulse to the X
7. Force the Port 2 pins with A5h .
Devices
Z86E02
Z86E04
Z86E08
Z86E09
be in a V
to allow the internal signal IRESET to go Low. See
conditions.
sequence can be sent. See Figure 6 and
in duration.
Unlock clock cycles are the X
not the internal Z8 SCLK cycles.
IL
Memory Size
state. Allow 50 ms minimum for the device to completely exit POR
IN
0.5 KB
1.0 KB
2.0 KB
4.0 KB
pin is in a V
P r o g r a m m i n g S p e c i f i c a t i o n
Last Address
IL
IN
state, force Port 2 pins with A5h .
. The clock pulses should be a minimum of 1µsec
01FFh
03FFh
07FFh
0FFFh
IN
pin.
IN
clock cycle entered by the programmer,
Table
Z8 CMOS OTP Microcontrollers
Z86E02/E04/E08/E09 SL1995
4.
Table 5
for POR
IN
pin must
5