mc68hc908gr8a Freescale Semiconductor, Inc, mc68hc908gr8a Datasheet - Page 59

• Manufacturer Part Number: mc68hc908gr8a
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

The following conditions apply when in manual mode:
4.3.6 Programming the PLL
The following procedure shows how to program the PLL.
Freescale Semiconductor
1. Choose the desired bus frequency, f
2. Calculate the desired VCO frequency (four times the desired bus frequency).
3. Choose a practical PLL (crystal) reference frequency, f
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•
•
•
•
ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual
mode, the ACQ bit must be clear.
Before entering tracking mode (ACQ = 1), software must wait a given time, t
4.8 Acquisition/Lock Time
control register (PCTL).
Software must wait a given time, t
clock source to CGMOUT (BCS = 1).
The LOCK bit is disabled.
CPU interrupts from the CGM are disabled.
Typically, the reference crystal is 4 MHz and R = 1.
Frequency errors to the PLL are corrected at a rate of f
this rate must be as fast as possible. The VCO frequency must be an integer multiple of this rate.
The relationship between the VCO frequency, f
P, the power of two multiplier, and N, the range multiplier, are integers.
In cases where desired bus frequency has some tolerance, choose f
either by other module requirements (such as modules which are clocked by CGMXCLK), cost
requirements, or ideally, as high as the specified range allows. See
Specifications. Choose the reference divider, R = 1. After choosing N and P, the actual bus
frequency can be determined using equation in 2 above.
When the tolerance on the bus frequency is tight, choose f
and R = 1. If f
practical choices of f
The round function in the following equations means that the real number
should be rounded to the nearest integer number.
RCLK
R
cannot meet this requirement, use the following equation to solve for R with
MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5
RCLK
=
round R
, and choose the f
Specifications), after turning on the PLL by setting PLLON in the PLL
MAX
f
AL
VCLKDES
f
, after entering tracking mode before selecting the PLL as the
×
VCLK
BUSDES
⎧
⎨
⎩
⎛
⎜
⎝
f
------------------------- -
VCLKDES
f
=
RCLK
NOTE
=
RCLK
.
2
----------- f
P
R
4
N
×
VCLK
(
⎞
⎟
⎠
f
that gives the lowest R.
BUSDES
RCLK
–
, and the reference frequency, f
integer
RCLK
)
RCLK
/R. For stability and lock time reduction,
RCLK
⎛
⎜
⎝
, and the reference divider, R.
f
------------------------- -
VCLKDES
f
RCLK
to an integer divisor of f
Chapter 19 Electrical
RCLK
⎞
⎟
⎠
⎫
⎬
⎭
to a value determined
ACQ
Functional Description
(see
RCLK
BUSDES
, is
,
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