mc68hc908gr8a Freescale Semiconductor, Inc, mc68hc908gr8a Datasheet - Page 69

• Manufacturer Part Number: mc68hc908gr8a
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

4.5.4 PLL Multiplier Select Register Low
The PLL multiplier select register low (PMSL) contains the programming information for the low byte of
the modulo feedback divider.
MUL7–MUL0 — Multiplier Select Bits
4.5.5 PLL VCO Range Select Register
The PLL VCO range select register (PMRS) contains the programming information required for the
hardware configuration of the VCO.
VRS7–VRS0 — VCO Range Select Bits
Freescale Semiconductor
These read/write bits control the low byte of the modulo feedback divider that selects the VCO
frequency multiplier, N. (See
be written when the PLLON bit in the PCTL is set. A value of $0000 in the multiplier select registers
configures the modulo feedback divider the same as a value of $0001. Reset initializes the register to
$40 for a default multiply value of 64.
These read/write bits control the hardware center-of-range linear multiplier L which, in conjunction with
E (see
hardware center-of-range frequency, f
PCTL is set. (See
4.3.3 PLL
Address: $0038
Address: $003A
For applications using 1–8 MHz reference frequencies, this register must
be reprogrammed before enabling the PLL. The reset value of this register
will cause applications using 1–8 MHz reference frequencies to become
unstable if the PLL is enabled without programming an appropriate value.
The programmed value must not allow the VCO clock to exceed 32 MHz.
See
proper value for PMSL.
The multiplier select bits have built-in protection such that they cannot be
written when the PLL is on (PLLON = 1).
Reset:
Reset:
Read:
Read:
Write:
Write:
4.3.6 Programming the PLL
Figure 4-7. PLL Multiplier Select Register Low (PMSL)
Circuits,
4.3.7 Special Programming
Figure 4-8. PLL VCO Range Select Register (PMRS)
MUL7
VRS7
Bit 7
Bit 7
0
0
MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5
4.3.6 Programming the
4.3.3 PLL Circuits
MUL6
VRS6
6
1
6
1
VRS
MUL5
VRS5
5
0
5
0
. VRS7–VRS0 cannot be written when the PLLON bit in the
for detailed instructions on choosing the
NOTE
NOTE
Exceptions.) A value of $00 in the VCO range select
and
MUL4
VRS4
4
0
4
0
PLL, and
4.3.6 Programming the
MUL3
VRS3
3
0
3
0
4.5.1 PLL Control
MUL2
VRS2
2
0
2
0
MUL1
VRS1
PLL.) MUL7–MUL0 cannot
1
0
1
0
Register), controls the
MUL0
VRS0
Bit 0
Bit 0
0
0
CGM Registers
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