mc68hc908jl16 Freescale Semiconductor, Inc, mc68hc908jl16 Datasheet - Page 141

• Manufacturer Part Number: mc68hc908jl16
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

10.2.2 Data Direction Register A (DDRA)
Data direction register A determines whether each port A pin is an input or an output. Writing a logic 1 to
a DDRA bit enables the output buffer for the corresponding port A pin; a logic 0 disables the output buffer.
DDRA[7:0] — Data Direction Register A Bits
Figure 10-4
When DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When DDRAx is a logic 0,
reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
Freescale Semiconductor
These read/write bits control port A data direction. Reset clears DDRA[7:0], configuring all port A pins
as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
shows the port A I/O logic.
Address: $0004
For those devices packaged in a 28-pin package, PTA7 is not connected.
DDRA7 should be set to a 1 to configure PTA7 as an output.
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Reset:
Read:
Write:
READ DDRA ($0004)
WRITE DDRA ($0004)
WRITE PTA ($0000)
READ PTA ($0000)
DDRA7
Bit 7
0
Figure 10-3. Data Direction Register A (DDRA)
DDRA6
6
0
RESET
MC68HC908JL16 Data Sheet, Rev. 1.1
Figure 10-4. Port A I/O Circuit
DDRA5
5
0
NOTE
NOTE
DDRA4
DDRAx
PTAx
4
0
DDRA3
3
0
DDRA2
2
0
PTAPUEx
DDRA1
1
0
To KBI
DDRA0
Bit 0
PTAx
0
Port A
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