mc68hc908jl16 Freescale Semiconductor, Inc, mc68hc908jl16 Datasheet - Page 181

• Manufacturer Part Number: mc68hc908jl16
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

16.2.3 CPU During Break Interrupts
The CPU starts a break interrupt by:
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
16.2.4 TIM During Break Interrupts
A break interrupt stops the timer counter.
16.2.5 COP During Break Interrupts
The COP is disabled during a break interrupt when V
16.2.6 Break Module Registers
These registers control and monitor operation of the break module:
16.2.6.1 Break Status and Control Register (BRKSCR)
The break status and control register contains break module enable and status bits.
BRKE — Break Enable Bit
BRKA — Break Active Bit
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This read/write bit enables breaks on break address register matches. Clear BRKE by writing a logic
zero to bit 7. Reset clears the BRKE bit.
This read/write status and control bit is set when a break address match occurs. Writing a logic one to
BRKA generates a break interrupt. Clear BRKA by writing a logic zero to it before exiting the break
routine. Reset clears the BRKA bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled
1 = Break address match
0 = No break address match
Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD in monitor mode)
Break status and control register (BRKSCR)
Break address register high (BRKH)
Break address register low (BRKL)
Break status register (BSR)
Break flag control register (BFCR)
Address: $FE0E
Reset:
Read:
Write:
Figure 16-3. Break Status and Control Register (BRKSCR)
BRKE
Bit 7
0
= Unimplemented
BRKA
6
0
MC68HC908JL16 Data Sheet, Rev. 1.1
5
0
0
4
0
0
TST
is present on the RST pin.
3
0
0
2
0
0
1
0
0
Break Module (BRK)
Bit 0
0
0
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