mc68hc908rf2 Freescale Semiconductor, Inc, mc68hc908rf2 Datasheet - Page 89

• Manufacturer Part Number: mc68hc908rf2
• Description: M68hc08 Microcontrollers Microcontroller / Transmitter
• Manufacturer: Freescale Semiconductor, Inc

MC68HC908RF2 — Rev. 4.0
MOTOROLA
CS — Clock Select Bit
ICGON — Internal Clock Generator On Bit
ICGS — Internal Clock Generator Stable Bit
ECGON — External Clock Generator On Bit
ECGS — External Clock Generator Stable Bit
This read/write bit determines which clock will generate the oscillator output
clock (CGMXCLK). This bit can be set when ECGON and ECGS have been set
for at least one bus cycle and can be cleared when ICGON and ICGS have been
set for at least one bus cycle. This bit is forced set when the clock monitor
determines the internal clock (ICLK) is inactive or when ICGON is clear. This bit
is forced clear when the clock monitor determines that the external clock (ECLK)
is inactive, when ECGON is clear, or during reset.
This read/write bit enables the internal clock generator. ICGON can be cleared
when the CS bit has been set and the CMON bit has been clear for at least one
bus cycle. ICGON is forced set when the CMON bit is set, the CS bit is clear, or
during reset.
This read-only bit indicates when the internal clock generator has determined
that the internal clock (ICLK) is within about 5 percent of the desired value. This
bit is forced clear when the clock monitor determines the ICLK is inactive, when
ICGON is clear, when the ICG multiplier factor is written, or during reset.
This read/write bit enables the external clock generator. ECGON can be cleared
when the CS and CMON bits have been clear for at least one bus cycle.
ECGON is forced set when the CMON bit or the CS bit is set. ECGON is forced
clear during reset.
This read-only bit indicates when at least 4096 external clock (ECLK) cycles
have elapsed since the external clock generator was enabled. This is not an
assurance of the stability of ECLK but is meant to provide a startup delay. This
bit is forced clear when the clock monitor determines ECLK is inactive, when
ECGON is clear, or during reset.
1 = External clock (ECLK) sources CGMXCLK
0 = Internal clock (ICLK) sources CGMXCLK
1 = Internal clock generator enabled
0 = Internal clock generator disabled
1 = Internal clock is within 5 percent of the desired value.
0 = Internal clock may not be within 5 percent of the desired value.
1 = External clock generator enabled
0 = External clock generator disabled
1 = 4096 ECLK cycles have elapsed since ECGON was set.
0 = External cock is unstable, inactive, or disabled.
Freescale Semiconductor, Inc.
For More Information On This Product,
Internal Clock Generator Module (ICG)
Go to: www.freescale.com
Internal Clock Generator Module (ICG)
I/O Registers
Data Sheet
89