mc68hc908rk2 Freescale Semiconductor, Inc, mc68hc908rk2 Datasheet

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... MC68HC908RK2/D REV 4 MC68HC908RK2 Advance Information HCMOS Microcontroller Unit ...

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... Motorola was negligent regarding the design or manufacture of the part. Motorola, Inc Equal Opportunity/Affirmative Action Employer. Motorola and are registered trademarks of Motorola, Inc. DigitalDNA is a trademark of Motorola, Inc. MC68HC908RK2 — Rev. 4.0 MOTOROLA © Motorola, Inc., 2001 Advance Information 3 ...

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... December, Section 15. Timer Interface Module (TIM) 4 2001 discrepancies corrected throughout this section. Advance Information 4 Revision History Description 15.6 Interrupts — V and V specifications LVS LVR — Maximum value for FLASH — Timer Page Number(s) 205 214 224 225 195 MC68HC908RK2 — Rev. 4.0 MOTOROLA ...

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... Section 13. Input/Output (I/O) Ports . . . . . . . . . . . . . . . 173 Section 14. Keyboard/External Interrupt Section 15. Timer Interface Module (TIM 195 Section 16. Preliminary Electrical Specifications . . . . 217 Section 17. Mechanical Specifications . . . . . . . . . . . . . 227 Section 18. Ordering Information . . . . . . . . . . . . . . . . . 229 MC68HC908RK2 — Rev. 4.0 MOTOROLA Module (COP 161 Module (KBI 181 List of Sections List of Sections Advance Information ...

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... List of Sections Advance Information 6 List of Sections MC68HC908RK2 — Rev. 4.0 MOTOROLA ...

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... MC68HC908RK2 — Rev. 4.0 MOTOROLA Section 1. General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Power Supply Pins (V DD Oscillator Pins (OSC1 and OSC2 .28 External Reset (RST External Interrupt Pin (IRQ1 .28 Port A Input/Output Pins (PTA7, PTA6/KBD6–PTA1/KBD1, and PTA0 Port B Input/Output Pins (PTB5, PTB4/TCH1, PTB3/TCLK, PTB2/TCH0, PTB1, and PTB0/MCLK) ...

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... PRGRNGE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 ERARNGE Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 REDPROG Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Example Routine Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Section 5. Central Processor Unit (CPU) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table of Contents MC68HC908RK2 — Rev. 4.0 MOTOROLA ...

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... MC68HC908RK2 — Rev. 4.0 MOTOROLA Arithmetic/Logic Unit (ALU Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Section 6. System Integration Module (SIM) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . 83 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . . . 83 Clocks in Stop Mode and Wait Mode ...

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... Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Section 8. Internal Clock Generator Module (ICG) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Clock Enable Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Internal Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Digitally Controlled Oscillator . . . . . . . . . . . . . . . . . . . . . 112 Modulo N Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Frequency Comparator . . . . . . . . . . . . . . . . . . . . . . . . . 112 Table of Contents MC68HC908RK2 — Rev. 4.0 MOTOROLA ...

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... MC68HC908RK2 — Rev. 4.0 MOTOROLA Digital Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 External Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . 114 External Oscillator Amplifier . . . . . . . . . . . . . . . . . . . . . . 114 External Clock Input Path . . . . . . . . . . . . . . . . . . . . . . .115 Clock Monitor Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Clock Monitor Reference Generator . . . . . . . . . . . . . . . 116 Internal Clock Activity Detector . . . . . . . . . . . . . . . . . . . 119 External Clock Activity Detector . . . . . . . . . . . . . . . . . . .119 Clock Selection Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 Clock Selection Switch ...

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... Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Section 11. Computer Operating Properly Module (COP) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 CGMXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Reset Vector Fetch 164 Table of Contents MC68HC908RK2 — Rev. 4.0 MOTOROLA ...

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... MC68HC908RK2 — Rev. 4.0 MOTOROLA COPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 COPRS 164 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Interrupts 165 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 COP Module During Break Interrupts . . . . . . . . . . . . . . . . . . .166 Section 12. Low-Voltage Inhibit (LVI) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Functional Description ...

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... TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . .199 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .200 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . 201 Pulse-Width Modulation (PWM 201 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . 202 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . 203 PWM Initialization 204 Table of Contents MC68HC908RK2 — Rev. 4.0 MOTOROLA ...

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... Internal Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . 223 16.11 LVI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 16.12 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 MC68HC908RK2 — Rev. 4.0 MOTOROLA Interrupts 205 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 206 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 TIM Clock Pin (TCLK 207 TIM Channel I/O Pins (TCH0 and TCH1 .207 I/O Registers ...

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... Table of Contents 17.1 17.2 17.3 17.4 18.1 18.2 18.3 Advance Information 16 Section 17. Mechanical Specifications Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 20-Pin Plastic SSOP Package (Case No. 940C-03 228 20-Pin SOIC Plastic Package (Case No. 751D-05 228 Section 18. Ordering Information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 Table of Contents MC68HC908RK2 — Rev. 4.0 MOTOROLA ...

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... Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6-11 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . . . 93 MC68HC908RK2 — Rev. 4.0 MOTOROLA Title MC68HC908RK2 MCU Block Diagram . . . . . . . . . . . . . . . . . . 26 SSOP/SOIC Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . 27 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Memory Map Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . . 34 FLASH 2TS Control Register (FLCR .45 Smart Programming Algorithm Flowchart FLASH 2TS Block Protect Register (FLBPR CPU Registers ...

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... Clock Selection Circuit Block Diagram . . . . . . . . . . . . . . . . . . 120 Synchronizing Clock Switcher Circuit Diagram 121 Code Example for Switching Clock Sources . . . . . . . . . . . . . 123 Code Example for Enabling the Clock Monitor . . . . . . . . . . . . 124 Code Example for Writing DDIV and DSTG . . . . . . . . . . . . . .133 Configuration Register (CONFIG 146 List of Figures Page MC68HC908RK2 — Rev. 4.0 MOTOROLA ...

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... TIM Counter Modulo Registers (TMODH and TMODL 211 15-7 TIM Channel Status and Control Registers 15-8 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 15-9 TIM Channel 0 Registers (TCH0H and TCH0L 216 15-10 TIM Channel 1 Registers (TCH1H and TCH1L 216 MC68HC908RK2 — Rev. 4.0 MOTOROLA Title Register (INTKBSCR 191 (TSC0 and TSC1 212 ...

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... List of Figures Advance Information 20 MC68HC908RK2 — Rev. 4.0 List of Figures MOTOROLA ...

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... WRITE (Write Memory) Command 156 10-5 IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . . . 156 10-6 IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . . 157 10-7 READSP (Read Stack Pointer) Command . . . . . . . . . . . . . . . 157 10-8 RUN (Run User Program) Command . . . . . . . . . . . . . . . . . . .158 12-1 LOWV Bit Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 MC68HC908RK2 — Rev. 4.0 MOTOROLA Title Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Charge Pump Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . .47 Erase Block Sizes Embedded FLASH Routines ...

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... List of Tables Table 13-1 Port A Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 13-2 Port B Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 15-1 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 15-2 Prescaler Selection .210 15-3 Mode, Edge, and Level Selection . . . . . . . . . . . . . . . . . . . . . . 214 18-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 Advance Information 22 Title MC68HC908RK2 — Rev. 4.0 List of Tables Page MOTOROLA ...

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... Introduction The MC68HC908RK2 MCU is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). Optimized for low-power operation and available in a small 20-pin SSOP/SOIC package, this MCU is well suited for remote keyless entry (RKE) transmitter designs. The M68HC08 Family is based on the customer-specified integrated circuit (CSIC) design strategy ...

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... General Description 1.3 Features Features of the MC68HC908RK2 MCU include: • • • • • • • • • • • • • security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH difficult for unauthorized users. Advance Information ...

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... Memory-to-memory data transfers Fast 8 8 multiply instruction Fast 16/8 divide instruction Binary-coded decimal (BCD) instructions Optimization for controller applications Third party C language support shows the structure of the MC68HC908RK2 MCU. General Description General Description MCU Block Diagram Advance Information 25 ...

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... POWER-ON RESET MODULE V DD POWER PIN CONTAINS INTEGRATED PULLUP RESISTOR ** HIGH CURRENT SINK PIN ‡ PIN CONTAINS SOFTWARE SELECTABLE PULLUP RESISTOR Figure 1-1. MC68HC908RK2 MCU Block Diagram INTERNAL BUS SECURITY MODULE COMPUTER OPERATING PROPERLY MODULE LOW-VOLTAGE INHIBIT MODULE 2-CHANNEL TIMER MODULE PTA7** ‡ ...

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... To prevent noise problems, take special care to provide power supply bypassing at the MCU as shown in Figure as possible. Use high-frequency-response ceramic capacitors for C Bypass applications that require the port pins to source high current levels. MC68HC908RK2 — Rev. 4.0 MOTOROLA shows the pin assignments. PTA0 1 PTB0/MCLK 2 ...

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... IRQ1 is an asynchronous external interrupt pin. The IRQ1 pin contains an internal pullup resistor. Advance Information 28 MCU Bypass 0 Bulk V DD Note: Component values shown represent typical applications. Figure 1-3. Power Supply Bypassing Section 6. System Integration Module General Description V SS MC68HC908RK2 — Rev. 4.0 MOTOROLA ...

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... All port A pins are high-current sink pins. 1.5.6 Port B Input/Output Pins (PTB5, PTB4/TCH1, PTB3/TCLK, PTB2/TCH0, PTB1, and PTB0/MCLK) Port 6-bit, general-purpose, bidirectional I/O port, with some of its pins shared with the timer (TIM) module. MC68HC908RK2 — Rev. 4.0 MOTOROLA General Description General Description Pin Assignments ...

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... General Description Advance Information 30 General Description MC68HC908RK2 — Rev. 4.0 MOTOROLA ...

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... These definitions apply to the memory map representation of reserved and unimplemented locations: • • MC68HC908RK2 — Rev. 4.0 MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Input/Output Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Figure 2031 bytes of user FLASH memory 128 bytes of random-access memory (RAM) 14 bytes of user-defined vectors in FLASH memory 768 bytes of monitor read-only memory (ROM) Reserved — ...

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... BREAK ADDRESS REGISTER HIGH (BRKH) $FE0D BREAK ADDRESS REGISTER LOW (BRKL) 1. Address $7FEF is reserved for an optional factory-determined ICG trim value. Consult with a local Motorola representative for more information and availability of this option. Figure 2-1. Memory Map Memory Map (1) MC68HC908RK2 — Rev. 4.0 MOTOROLA ...

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... Additional I/O registers have these addresses: • • • • • • • • • • MC68HC908RK2 — Rev. 4.0 MOTOROLA $FE0E BREAK STATUS AND CONTROL REGISTER (BSCR) $FE0F LVI STATUS REGISTER (LVISR) $FE10 UNIMPLEMENTED (222 BYTES) $FEEF $FEF0 MONITOR ROM (16 BYTES) $FEFF ...

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... Memory Map Bit 0 PTA3 PTA2 PTA1 PTA0 PTB3 PTB2 PTB1 PTB0 DDRA3 DDRA2 DDRA1 DDRA0 DDRB3 DDRB2 DDRB1 DDRB0 KEYF 0 IMASKK MODEK R ACKK KBIE3 KBIE2 KBIE1 Reserved U = Unaffected X = Indeterminate MC68HC908RK2 — Rev. 4.0 MOTOROLA ...

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... Register Low (TMODL) Write: See page 211. Reset: Read: Timer Channel 0 Status and Control Register $0025 Write: (TSC0) See page 212. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908RK2 — Rev. 4.0 MOTOROLA Bit EXTSLOW LVISTOP LVIRST LVIPWR TOF TOIE ...

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... Unimplemented R Memory Map Bit Bit Bit 0 ELS1B ELS1A TOV1 CH1MAX Bit Bit 0 ICGS ECGS ICGON ECGON Reserved U = Unaffected X = Indeterminate MC68HC908RK2 — Rev. 4.0 MOTOROLA ...

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... Write: See page 98. POR: Read: SIM Break Flag Control $FE02 Register (SBFCR) Write: See page 99. Reset: $FE03 Reserved Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908RK2 — Rev. 4.0 MOTOROLA Bit TRIM7 TRIM6 TRIM5 TRIM4 ...

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... Unimplemented R Memory Map Bit HVEN MARGIN ERASE PGM Bit Bit Reserved U = Unaffected X = Indeterminate MC68HC908RK2 — Rev. 4.0 MOTOROLA ...

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... See page 52. Reset: † Non-volatile FLASH register Read: COP Control Register $FFFF (COPCTL) Write: See page 165. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet Table 2-1 MC68HC908RK2 — Rev. 4.0 MOTOROLA Bit Unaffected by reset Low byte of reset vector ...

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... The address range $F000–F2EF is reserved for the monitor code functions, FLASH memory programming, and erase algorithms. The address range $FEF0–$FEFF holds reserved ROM addresses that contain the monitor code reset vectors. Advance Information 40 MC68HC908RK2 — Rev. 4.0 Memory Map MOTOROLA ...

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... The stack pointer decrements during pushes and increments during pulls. NOTE: Be careful when using nested subroutines. The CPU could overwrite data in the RAM during a subroutine or during the interrupt stacking operation. MC68HC908RK2 — Rev. 4.0 MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Random-Access Memory (RAM) Advance Information ...

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... Random-Access Memory (RAM) Advance Information 42 Random-Access Memory (RAM) MC68HC908RK2 — Rev. 4.0 MOTOROLA ...

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... This section describes the operation of the embedded FLASH 2TS memory. This memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump. MC68HC908RK2 — Rev. 4.0 MOTOROLA Section 4. FLASH 2TS Memory Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Functional Description ...

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... Details for these operations appear later in this section. Memory in the FLASH 2TS array is organized into pages within rows. For the 2-Kbyte array on the MC68HC908RK2, the page size is one byte. There are eight pages (or eight bytes) per row. Programming operations are performed on a page basis, one byte at time ...

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... This read/write bit selects the factor by which the charge pump clock is divided from the system clock. See Frequency 1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or copying the FLASH 2TS difficult for unauthorized users. MC68HC908RK2 — Rev. 4.0 MOTOROLA $FE08 Bit 7 6 ...

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... High voltage enabled to array and charge pump High voltage disabled to array and charge pump off 1 = Margin read operation selected 0 = Margin read operation unselected 1 = Erase operation selected 0 = Erase operation unselected 1 = Program operation selected 0 = Program operation unselected FLASH 2TS Memory for a description for a description MC68HC908RK2 — Rev. 4.0 MOTOROLA ...

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... Ensure target portion of array is unprotected by reading the block 3. Write to any FLASH 2TS address with any data within the block 4. Set the HVEN bit. 5. Wait for a time Clear the HVEN bit. MC68HC908RK2 — Rev. 4.0 MOTOROLA Table 4-1. Charge Pump Clock Frequency FDIV0 Pump Clock Frequency ...

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... Table 4-2. Erase Block Sizes BLK1 BLK0 Block Size, Addresses Cared FLASH 2TS Memory Full array: 2 Kbytes One-half array: 1 Kbytes Eight rows: 64 bytes Single row: 8 bytes (Figure 4-2) is MC68HC908RK2 — Rev. 4.0 MOTOROLA ...

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... NOTE: While these operations must be performed in the order shown, other unrelated operations may occur between the steps. The smart programming algorithm guarantees the minimum possible program time. MC68HC908RK2 — Rev. 4.0 MOTOROLA frequency. and enables the latching of address and data for programming. . ...

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... STEP CLEAR HVEN BIT WAIT T HVTV SET MARGIN BIT WAIT t VTP CLEAR PGM BIT WAIT t HVD MARGIN READ PAGE OF DATA N MARGIN READ DATA EQUAL TO WRITE DATA? Y CLEAR MARGIN BIT CLEAR INTERRUPT MASK: CLI INSTRUCTION PROGRAMMING OPERATION COMPLETE MC68HC908RK2 — Rev. 4.0 MOTOROLA ...

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... IRQ1 pin. The presence of V allows entry into monitor mode out of reset. Therefore, the ability to change the block protect register is voltage-level dependent and can occur in either user or monitor modes. MC68HC908RK2 — Rev. 4.0 MOTOROLA Register. The block protect register FLASH 2TS Memory ...

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... Address range protected from erase or program 0 = Address range open to erase or program 1 = Address range protected from erase or program 0 = Address range open to erase or program 1 = Address range protected from erase or program 0 = Address range open to erase or program FLASH 2TS Memory Bit 0 BPR3 BPR2 BPR1 BPR0 MC68HC908RK2 — Rev. 4.0 MOTOROLA ...

Page 53

... Embedded Program/Erase Routines The MC68HC908RK2 monitor ROM contains numerous routines for programming and erasing the FLASH memory. These embedded routines are intended to assist the programmer with modifying the FLASH memory array. These routines will implement the smart ...

Page 54

... RAM only (length is user determined) Non-zero for read/verify to RAM, 0 for output to PA0 Set if good compare for read/verify to RAM only Contains checksum Contains read FLASH data for read/verify to RAM only FLASH 2TS Memory (1) Variable Address RAMSTART + 8 RAMSTART + 9 RAMSTART + 10 RAMSTART + 12 RAMSTART + 13 RAMSTART + 15 MC68HC908RK2 — Rev. 4.0 MOTOROLA ...

Page 55

... This routine programs a range of FLASH defined by H:X and LADDR. The range can be from one byte to as much RAM as can be allocated to DATA. The smart programming algorithm defined in Program/Margin Read Operation MC68HC908RK2 — Rev. 4.0 MOTOROLA Contains the first address in the range Contains the last address in the range ...

Page 56

... CPU frequency times 4 in MHz Table 4-5. CTLBYTE-Erase Block Size Bit 6 Bit Set, masking interrupts. 4.6 FLASH 2TS Erase Operation FLASH 2TS Memory Table 4-5) Block Size Full array One half array Eight rows: 64 pages Single row: 8 pages is used. MC68HC908RK2 — Rev. 4.0 MOTOROLA ...

Page 57

... REDPROG routine. All rows in the range will be programmed once before any are programmed again. This approach is taken to ensure that all rows reach the end of lifetime at approximately the same time. MC68HC908RK2 — Rev. 4.0 MOTOROLA Contains the address of the first row in the range. This ...

Page 58

... RAM Definitions for Subroutines ;************************************************************** ORG CTRLBYT CPUSPD LADDR BUMPS DERASE ;Allocation of “DATA” space is dependent on the device and ;application Advance Information 58 EQU $80 EQU $F000 EQU $F003 EQU $F006 EQU $F009 RAM+8 RMB 1 RMB 1 RMB 2 RMB 1 RMB 2 FLASH 2TS Memory MC68HC908RK2 — Rev. 4.0 MOTOROLA ...

Page 59

... MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV LDHX STHX LDHX JSR MC68HC908RK2 — Rev. 4.0 MOTOROLA RMB 8 #$FF ;TARGET IS RAM #$7807 ;END AFTER FIRST ROW LADDR #$7800 ;START AT FIRST ROW RDVRRNG ;DATA WILL CONTAIN FLASH INFO #$08,CPUSPD ;Load Bus frequency in MHz * 4 #$60,CTRLBYT ...

Page 60

... DERASE #$7808 ;Load the last address of the multi-row ;range; (in this case, 2 rows) LADDR ;into LADDR #$7800 ;Load the first address of the ;multi-row range into H:X REDPROG ;Call through jump table. FLASH 2TS Memory MC68HC908RK2 — Rev. 4.0 MOTOROLA ...

Page 61

... HVEN = 1), then it will remain in that mode during stop. Exit from stop mode now must be done with a reset rather than an interrupt because if exiting stop with an interrupt, the memory will not be in read mode and the interrupt vector cannot be read from the memory. MC68HC908RK2 — Rev. 4.0 MOTOROLA FLASH 2TS Memory FLASH 2TS Memory ...

Page 62

... FLASH 2TS Memory Advance Information 62 FLASH 2TS Memory MC68HC908RK2 — Rev. 4.0 MOTOROLA ...

Page 63

... Advance Information — MC68HC908RK2 5.1 Contents 5.2 5.3 5.4 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.5 5.6 5.6.1 5.6.2 5.7 5.8 5.9 MC68HC908RK2 Rev. 4.0 — MOTOROLA Section 5. Central Processor Unit (CPU) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Arithmetic/Logic Unit (ALU Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Instruction Set Summary ...

Page 64

... Enhanced binary-coded decimal (BCD) data handling Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes Low-power stop and wait modes shows the five CPU registers. CPU registers are not part of Central Processor Unit (CPU) MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 65

... H is the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index register. In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand. MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 66

... Figure 5-3. Index Register (H:X) Bit Figure 5-4. Stack Pointer (SP) Central Processor Unit (CPU MC68HC908RK2 Rev. 4.0 — MOTOROLA Bit 0 X Bit 0 1 ...

Page 67

... The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to logic 1. The following paragraphs describe the functions of the condition code register. Read: Write: Reset: MC68HC908RK2 Rev. 4.0 — MOTOROLA Bit 15 14 ...

Page 68

... Advance Information Overflow overflow 1 = Carry between bits 3 and carry between bits 3 and Interrupts disabled 0 = Interrupts enabled Central Processor Unit (CPU) MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 69

... Refer to the CPU08 Reference Manual, Motorola document oeswe number CPU08RM/AD, for a description of the instructions and addressing modes and more detail about the architecture of the CPU. 5.6 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. MC68HC908RK2 Rev. 4.0 — MOTOROLA 1 = Negative result 0 = Non-negative result ...

Page 70

... After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. Disables the CPU clock Section 7. Break Module provides a summary of the M68HC08 instruction set. Central Processor Unit (CPU) (BRK).) The MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 71

... BCLR n, opr Clear Bit BCS rel Branch if Carry Bit Set (Same as BLO) BEQ rel Branch if Equal Branch if Greater Than or Equal To BGE opr (Signed Operands) Branch if Greater Than (Signed BGT opr Operands) MC68HC908RK2 Rev. 4.0 — MOTOROLA Description A (A) + (M) + (C) A (A) + (M) « SP (SP) + (16 M) « ...

Page 72

... REL DIR (b0 DIR (b1 DIR (b2 DIR (b3 – – – – – DIR (b4 DIR (b5 DIR (b6 DIR (b7 MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 73

... CPHX #opr Compare H:X with M CPHX opr CPX #opr CPX opr CPX opr CPX ,X Compare X with M CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP DAA Decimal Adjust A MC68HC908RK2 Rev. 4.0 — MOTOROLA Description (PC push (PCL) SP (SP) – 1; push (PCH) SP (SP) – ...

Page 74

... SP1 9EE6 ff 4 SP2 9ED6 IMM – – – DIR IMM DIR EXT IX2 – – – IX1 SP1 9EEE ff 4 SP2 9EDE MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 75

... PULX Pull X from Stack ROL opr ROLA ROLX Rotate Left through Carry ROL opr,X ROL ,X ROL opr,SP ROR opr RORA RORX Rotate Right through Carry ROR opr,X ROR ,X ROR opr,SP MC68HC908RK2 Rev. 4.0 — MOTOROLA Description (M) (M) Destination ...

Page 76

... DIR EXT IX2 – – IX1 SP1 9EE0 ff 4 SP2 9ED0 – – 1 – – – INH INH 84 2 – – – – – – INH 97 1 MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 77

... Indexed, 8-bit offset addressing mode IX1+ Indexed, 8-bit offset, post increment addressing mode IX2 Indexed, 16-bit offset addressing mode M Memory location N Negative bit 5.9 Opcode Map The opcode map is provided in MC68HC908RK2 Rev. 4.0 — MOTOROLA Description A (CCR) (A) – $00 or (X) – $00 or (M) – $00 H:X (SP ...

Page 78

Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH INH MSB LSB BSET0 BRA NEG NEGA NEGX 0 BRSET0 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 ...

Page 79

... Advance Information — MC68HC908RK2 Section 6. System Integration Module (SIM) 6.1 Contents 6.2 6.3 6.3.1 6.3.2 6.3.3 6.4 6.4.1 6.4.2 6.4.2.1 6.4.2.2 6.4.2.3 6.4.2.4 6.4.2.5 6.5 6.5.1 6.5.2 6.5.3 6.6 6.6.1 6.6.1.1 6.6.1.2 6.6.2 6.6.3 6.6.4 6.7 6.7.1 6.7.2 MC68HC908RK2 Rev. 4.0 — MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . 83 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . . . 83 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . 84 Reset and System Initialization External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Active Resets from Internal Sources ...

Page 80

... Internal clock control Master reset control, including power-on reset (POR) and computer operating properly (COP) timeout Interrupt control: – Acknowledge timing – Arbitration control timing – Vector address generation CPU enable/disable timing System Integration Module (SIM) Figure 6-1. MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 81

... RESET PIN LOGIC SIM RESET STATUS REGISTER MC68HC908RK2 Rev. 4.0 — MOTOROLA STOP/WAIT CONTROL SIM COUNTER 2 CLOCK CLOCK GENERATORS CONTROL POR CONTROL MASTER RESET RESET PIN CONTROL CONTROL RESET INTERRUPT CONTROL AND PRIORITY DECODE Figure 6-1. SIM Block Diagram System Integration Module (SIM) ...

Page 82

... Signal from the power-on reset module to the SIM Internal reset signal Read/write signal System Integration Module (SIM Bit 0 SBSW R R See Note 0 ILAD 0 LVI Reserved X = Indeterminate Description MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 83

... ECLK CLOCK SELECT CIRCUIT ICLK ICG CS Generator PTB3 MONITOR MODE USER MODE ICG MC68HC908RK2 Rev. 4.0 — MOTOROLA CGMXCLK A CGMOUT *When CGMOUT = B Figure 6-3. ICG Clock Signals System Integration Module (SIM) System Integration Module (SIM) ...

Page 84

... SIM reset status register (SRSR). (See Advance Information 84 Power-on reset module (POR) External Reset Pin (RST) Computer operating properly module (COP) Low-voltage inhibit module (LVI) Illegal opcode Illegal address System Integration Module (SIM) 6.7.2 Stop Mode.) 6.5 SIM Counter), but an 6.8 SIM Registers.) MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 85

... CGMXCLK cycles, assuming that neither the POR nor the LVI was the source of the reset. Figure 6-4 RST CGMOUT IAB PC Figure 6-4. External Reset Recovery Timing MC68HC908RK2 Rev. 4.0 — MOTOROLA shows the relative timing of an external reset recovery. PULLED LOW EXTERNAL PULLED HIGH EXTERNAL System Integration Module (SIM) ...

Page 86

... An internal reset can be caused by an illegal address, 6-5. RST PULLED LOW BY MCU 32 CYCLES Figure 6-5. Internal Reset Timing ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST LVI POR Figure 6-6. Sources of Internal Reset System Integration Module (SIM) Figure 6-6.) Note that 32 CYCLES VECTOR HIGH INTERNAL RESET MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 87

... OSC1 PORRST CYCLES CGMXCLK CGMOUT RST IAB MC68HC908RK2 Rev. 4.0 — MOTOROLA A POR pulse is generated. The internal reset signal is asserted. The SIM enables CGMOUT. Internal clocks to the CPU and modules are held inactive for 4096 CGMXCLK cycles to allow stabilization of the oscillator. ...

Page 88

... Section 12. Low-Voltage Inhibit Advance Information 88 (COP).) voltage falls to the V voltage. The LVI bit in the SIM reset DD LVR + H . Another 64 CGMXCLK cycles later, the CPU is LVR LVR (LVI).) System Integration Module (SIM) Section 11. Computer Operating DD MC68HC908RK2 Rev. 4.0 — MOTOROLA rises ...

Page 89

... SIM Counter and Reset States External reset has no effect on the SIM counter. See for details. The SIM counter is free-running after all reset states. See 6.4.2 Active Resets from Internal Sources internal reset recovery sequences. MC68HC908RK2 Rev. 4.0 — MOTOROLA System Integration Module (SIM) ...

Page 90

... Non-maskable software interrupt instruction (SWI) Figure 6-8 shows interrupt recovery timing. Figure 6-9.) SP – – – – – 1[15: CCR . Figure 6-8 Interrupt Entry System Integration Module (SIM) shows interrupt entry timing. VECT H VECT L START ADDR V DATA H V DATA L OPCODE MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 91

... YES AS MANY INTERRUPTS AS EXIST ON CHIP MC68HC908RK2 Rev. 4.0 — MOTOROLA FROM RESET YES BREAK INTERRUPT? I BIT SET BIT SET? NO YES IRQ INTERRUPT? NO LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI YES INSTRUCTION? NO YES RTI UNSTACK CPU REGISTERS INSTRUCTION? NO Figure 6-9. Interrupt Processing ...

Page 92

... H register and then restore it prior to exiting the routine. Advance Information 92 SP – – – – 1 [15:8] PC – 1 [7:0] Figure 6-10. Interrupt Recovery System Integration Module (SIM OPCODE OPERAND Figure 6-11 MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 93

... Break Interrupts The break module can stop normal program flow at a software- programmable break point by asserting its break interrupt output. (See Section 7. Break Module state by forcing it to the SWI vector location. Refer to the break interrupt MC68HC908RK2 Rev. 4.0 — MOTOROLA CLI LDA ...

Page 94

... A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled. Stacking for the interrupt begins one Advance Information 94 Figure 6-12 shows the timing for wait mode System Integration Module (SIM) MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 95

... If the COP disable bit, COPD, in the mask option register is logic 0, then the computer operating properly module (COP) is enabled and remains active in wait mode. R/W Figure 6-13 EXITSTOPWAIT Note: EXITSTOPWAIT = CGMXCLK MC68HC908RK2 Rev. 4.0 — MOTOROLA IAB WAIT ADDR WAIT ADDR + 1 IDB PREVIOUS DATA Note: Previous data can be operand data or the WAIT opcode, depending on the last instruction ...

Page 96

... IAB STOP ADDR STOP ADDR + 1 IDB PREVIOUS DATA NEXT OPCODE R/W . instruction Figure 6-15. Stop Mode Entry Timing STOP RECOVERY PERIOD STOP + 2 STOP + 2 System Integration Module (SIM) SAME SAME SAME SAME SP SP – – – 3 MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 97

... BRCLR SBSW, SBSR, RETURN TST LOBYTE,SP BNE DOLO DEC HIBYTE,SP DOLO DEC LOBYTE,SP RETURN PULH RTI MC68HC908RK2 Rev. 4.0 — MOTOROLA SIM break status register, SBSR SIM reset status register, SRSR SIM break flag control register, SBFCR $FE00 Bit Reserved Figure 6-17 ...

Page 98

... Last reset caused by an illegal opcode 0 = Read of SRSR 1 = Last reset caused by an opcode fetch from an illegal address 0 = Read of SRSR 1 = Last reset was caused by the LVI circuit 0 = Read of SRSR System Integration Module (SIM Bit 0 ILAD 0 LVI MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 99

... BCFE — Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU break state. To clear status bits during the break state, the BCFE bit must be set. MC68HC908RK2 Rev. 4.0 — MOTOROLA $FE02 ...

Page 100

... System Integration Module (SIM) Advance Information 100 System Integration Module (SIM) MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 101

... Advance Information — MC68HC908RK2 7.1 Contents 7.2 7.3 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.5 7.5.1 7.5.2 7.6 7.6.1 7.6.2 7.2 Introduction The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. 7.3 Features Features of the break module (BRK) include: • • • • MC68HC908RK2 Rev. 4.0 — MOTOROLA Section 7. Break Module (BRK) Introduction ...

Page 102

... Software writes a logic 1 to the BRKA bit in the break status and control register. Figure 7-1 shows the structure of the break module. IAB[15:8] BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR IAB[15:0] 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW IAB[7:0] Figure 7-1. Break Module Block Diagram Break Module (BRK) CONTROL BREAK MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 103

... CPU During Break Interrupts The CPU starts a break interrupt by: • • The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately. MC68HC908RK2 Rev. 4.0 — MOTOROLA Bit ...

Page 104

... Break Module Registers These registers control and monitor operation of the break module: • • • Advance Information 104 Break status and control register, BSCR Break address register high, BRKH Break address register low, BRKL Break Module (BRK) is present on the HI MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 105

... Clear BRKE by writing a logic 0 to bit 7. Reset clears the BRKE bit. BRKA — Break Active Bit This read/write status and control bit is set when a break address match occurs. Writing a logic 1 to BRKA generates a break interrupt. Clear BRKA by writing a logic before exiting the break routine. MC68HC908RK2 Rev. 4.0 — MOTOROLA $FE0E ...

Page 106

... Advance Information 106 Bit Bit Bit Bit Break Module (BRK Bit Bit Bit Bit MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 107

... Advance Information — MC68HC908RK2 Section 8. Internal Clock Generator Module (ICG) 8.1 Contents 8.2 8.3 8.4 8.4.1 8.4.2 8.4.2.1 8.4.2.2 8.4.2.3 8.4.2.4 8.4.3 8.4.3.1 8.4.3.2 8.4.4 8.4.4.1 8.4.4.2 8.4.4.3 8.4.5 8.4.5.1 8.4.5.2 8.5 8.5.1 8.5.2 8.5.3 8.5.4 8.5.4.1 8.5.4.2 8.5.4.3 8.5.4.4 8.5.5 MC68HC908RK2 Rev. 4.0 — MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Clock Enable Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Internal Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Digitally Controlled Oscillator . . . . . . . . . . . . . . . . . . . . . 112 Modulo N Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Frequency Comparator . . . . . . . . . . . . . . . . . . . . . . . . . 112 Digital Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 External Clock Generator ...

Page 108

... ICG DCO Divider Register . . . . . . . . . . . . . . . . . . . . . . . . . 143 ICG DCO Stage Register . . . . . . . . . . . . . . . . . . . . . . . . . . 144 External clock generator, either 1-pin external source or 2-pin crystal Internal clock generator with programmable frequency output in integer multiples of a nominal frequency (307.2 kHz 25 percent) Internal Clock Generator Module (ICG) MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 109

... The external clock enable signal (ECGEN) turns on the external clock generator which generates ECLK. ECGEN is set (active) whenever the ECGON bit is set and the ICGSTOP signal is clear. When ECGEN is clear, ECLK is low. MC68HC908RK2 Rev. 4.0 — MOTOROLA Frequency adjust (trim) register to improve variability to 2 percent ...

Page 110

... EXTERNAL CLOCK GENERATOR OSC1 OSC2 CONFIGURATION REGISTER BIT TOP LEVEL SIGNAL Internal Clock Generator Module (ICG) CGMOUT CGMXCLK IOFF EOFF CPU_INT CMF ECGS ICGS DDIV DSTG ICLK IBASE ICGEN ECGEN ECLK NAME REGISTER BIT NAME MODULE SIGNAL MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 111

... ICGEN VOLTAGE & CURRENT REFERENCES Figure 8-2. Internal Clock Generator Block Diagram MC68HC908RK2 Rev. 4.0 — MOTOROLA ) of 307.2 kHz 25 percent, and an internal clock (ICLK) which is A digitally controlled oscillator A modulo N divider A frequency comparator, which contains voltage and current references, a frequency to voltage converter, and comparators ...

Page 112

... The dependence of these outputs on the capacitor size, current reference, and voltage reference causes percent error in f Advance Information 112 8.5.4 Quantization Error in DCO . NOM Internal Clock Generator Module (ICG NOM . First, the frequency NOM MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 113

... NOM 1.05 f < IBASE NOM IBASE < 1.15 f NOM 1.15 f < IBASE NOM x: Maximum error is independent of value in DDIV[3:0]. DDIV increments or decrements when an addition to DSTG[7:0] carries or borrows. MC68HC908RK2 Rev. 4.0 — MOTOROLA Current to New Correction DDIV[3:0]:DSTG[7:0] Min $xFF to $xDF –32 (–$020) Max $x20 to $x00 ...

Page 114

... AMPLIFIER EXTERNAL CLOCK GENERATOR OSC1 Internal Clock Generator Module (ICG) Figure 8-3, contains an ECLK OSC2 *R can be 0 (shorted) when used S with higher-frequency crystals. * Refer to manufacturer’s data. S COMPONENTS REQUIRED FOR EXTERNAL CRYSTAL USE ONLY 2 MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 115

... Using the clock monitor requires both clocks to be active (ECGON and ICGON are both set). To enable the clock monitor, both clocks must also be stable (ECGS and ICGS both set). This is to prevent the use of the clock monitor when a clock is first turned on and potentially unstable MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 116

... Advance Information 116 Clock monitor reference generator Internal clock activity detector External clock activity detector Internal Clock Generator Module (ICG) Figure 8-4, contains these blocks: Table 8-2. Note that each Table 8-2, the MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 117

... CMON IBASE ICGEN EXTSLOW STOP ECGON ECLK NAME NAME Figure 8-4. Clock Monitor Block Diagram MC68HC908RK2 Rev. 4.0 — MOTOROLA CMON FICGS ICLK ACTIVITY IBASE DETECTOR ICGEN EREF IBASE ICGON EXTXTALEN EXTSLOW ECGS DIVIDER ECGON ECLK ESTBCLK IREF ECLK ACTIVITY ECGEN ECLK DETECTOR ...

Page 118

... Internal Clock Generator Module (ICG) u off 1.875 kHz 76.8 kHz 1*4 +/– 25% 500 kHz 244 Hz 76.8 kHz 1*4 +/– 25% 1.953 kHz 75 Hz 4.8 kHz 16*4 +/– 25% +/– 25% MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 119

... ECGS is set on a falling edge of the external stabilization clock (ESTBCLK). This will be 4096 ECLK cycles after the external clock generator on bit (ECGON) is set. ECGS is cleared when the external clock generator is disabled (ECGON is clear) or when EOFF is set. MC68HC908RK2 Rev. 4.0 — MOTOROLA Internal Clock Generator Module (ICG) ...

Page 120

... IOFF IOFF SWITCHER EOFF EOFF FORCE_I RESET FORCE_E V SS NAME TOP LEVEL SIGNAL Figure 8-5. Clock Selection Circuit Block Diagram Internal Clock Generator Module (ICG) 8-5, contains two clock OUTPUT CGMXCLK DIV2 CGMOUT NAME REGISTER BIT NAME MODULE SIGNAL MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 121

... IOFF ICLK FORCE_I ECLK FORCE_E SELECT EOFF FORCE_I = Force internal; reset condition FORCE_E = Force external Figure 8-6. Synchronizing Clock Switcher Circuit Diagram MC68HC908RK2 Rev. 4.0 — MOTOROLA Figure 8-6). When the clock select bit is changed, the DFF DFF ...

Page 122

... Advance Information 122 Switching clock sources Enabling the clock monitor Using clock monitor interrupts Quantization error in DCO output Switching internal clock frequencies Nominal frequency settling time Improving frequency settling time Trimming frequency Internal Clock Generator Module (ICG) MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 123

... ECGS set, then CS set, then ICGON clear bne loop ;Keep looping until ICGON is clear. Figure 8-7. Code Example for Switching Clock Sources MC68HC908RK2 Rev. 4.0 — MOTOROLA 8-7. This code is for illustrative purposes only and does not Internal Clock Generator Module (ICG) ...

Page 124

... CMIE. CMIE wont set until CMON set; CMON ; won’t set until ICGON, ICGS, ECGON, ECGS set. ;Check if ECGS set, then CMON set, then CMIE set ;Keep looping until CMIE is set. Internal Clock Generator Module (ICG) Figure 8-8. This code is MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 125

... Variable-delay ring oscillator 3. Ring oscillator fine-adjust circuit Each of these blocks affects the clock period of the internal clock (ICLK). Since these blocks are controlled by the digital loop filter (DLF) outputs MC68HC908RK2 Rev. 4.0 — MOTOROLA Enable the clock monitor and clock monitor interrupts. ...

Page 126

... Internal Clock Generator Module (ICG) Q-ERR Bus Cycles ICLK 1 1.61%–2.94% 8 0.202%–0.368% 1 0.806%–1.47% 4 0.202%–0.368% 1 0.403%–0.735% 2 0.202%–0.368% 1 0.202%–0.368% 1 0.202%–0.368% 1 0.202%–0.368% MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 127

... Adjusting the DSTG[0] bit has a 0.202 percent to 0.368 percent effect on the output clock period. This corresponds to the minimum size correction made by the DLF, and the inherent, long-term quantization error in the output frequency. MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 128

... If desired, switch to the external clock (see 4. Change the value Switch back to internal (see 6. Turn on the clock monitor (see Advance Information 128 Sources). 8.5.1 Switching Clock if desired. Monitor), if desired. Internal Clock Generator Module (ICG) 8.5.1 Switching Clock Sources), 8.5.2 Enabling the Clock MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 129

... That is, when transitioning from fast to slow: • • • MC68HC908RK2 Rev. 4.0 — MOTOROLA ), and since ICLK is N (the ICG multiply factor for the desired IBASE ...

Page 130

... IBASE abs 44 tot 1 Internal Clock Generator Module (ICG) , where x is the ICLKFAST x happens – this point, the IBASE IBASE IBASE – 128 2 IBASE MC68HC908RK2 Rev. 4.0 — MOTOROLA ) ...

Page 131

... The initial clock period can be expressed as in the next example, where t constant and DDIV1 and DSTG1 are the values of DDIV and DSTG when operating at t MC68HC908RK2 Rev. 4.0 — MOTOROLA , t ...

Page 132

... DVFACT int DDIV2 = DDIV1 = -------------------------------------- - DSFACT DDIV2 2 = DSTG2 DSFACT DSTG1 = + DDIV2 DDIV2 1 Figure 8-9. This example is for illustrative purposes only and Internal Clock Generator Module (ICG log 2 1 --------------------------- - log 2 + DVFACT – DDIV1 DSTG2 = ----------------- - DSTG2 2 MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 133

... These dependencies are in the voltage and current references, the offset of the comparators, and the internal capacitor. The voltage and temperature dependencies have been designed maximum of approximately 1 percent error. The process dependencies account for the rest. MC68HC908RK2 Rev. 4.0 — MOTOROLA ;DDIV and DSTG modification code example ...

Page 134

... It is recommended that the user preserve a copy of the contents of the ICG trim register (ICGTR) in non-volitale memory. Address $7FEF is reserved for an optional factory-determined value. Consult with a local Motorola representative for more information and availability of this option. Advance Information 134 Internal Clock Generator Module (ICG) MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 135

... One configuration register option affects the functionality of the ICG: EXTSLOW (slow external clock). All configuration register options will have a default setting. Refer to Section 9. Configuration Register (CONFIG) register is used. MC68HC908RK2 Rev. 4.0 — MOTOROLA Internal Clock Generator Module (ICG) Internal Clock Generator Module (ICG) ...

Page 136

... A summary of this interaction is shown in Table Advance Information 136 ICG control register, ICGCR ICG multiplier register, ICGMR ICG trim register, ICGTR ICG DCO divider control register, ICGDVR ICG DCO stage control register, ICGDSR 8-5. Internal Clock Generator Module (ICG) Figure 8-10. These MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 137

... Reset: Read: CG DCO Divider Control I $0039 Register (ICGDVR) Write: See page 143. Reset: Read: ICG DCO Stage Register $003A (ICGDSR) Write: See page 144. Reset: Figure 8-10. ICG I/O Register Summary MC68HC908RK2 Rev. 4.0 — MOTOROLA Bit CMF CMIE CMON ...

Page 138

... MC68HC908RK2 Rev. 4.0 — MOTOROLA — uw — — — uw — uw — — — ...

Page 139

... CMON — Clock Monitor On Bit This read/write bit enables the clock monitor. CMON can be set when both ICLK and ECLK have been on and stable for at least one bus cycle (ICGON, ECGON, ICGS, and ECGS are all set). CMON is MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 140

... External clock (ECLK) sources CGMXCLK 0 = Internal clock (ICLK) sources CGMXCLK 1 = Internal clock generator enabled 0 = Internal clock generator disabled 1 = Internal clock is within 5 percent of the desired value Internal clock may not be within 5 percent of the desired value. Internal Clock Generator Module (ICG) MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 141

... N. A value of $00 in this register is interpreted the same as a value of $01. This register cannot be written when the CMON bit is set. Reset sets this factor to $15 (decimal 21) for default frequency of 6.45 MHz 25 percent (1.613 MHz 25 percent bus). MC68HC908RK2 Rev. 4.0 — MOTOROLA 1 = External clock generator enabled 0 = External clock generator disabled 1 = 4096 ECLK cycles have elapsed since ECGON was set ...

Page 142

... Consult with a local Motorola representative for more information and availability of this option. Advance Information 142 Bit TRIM7 TRIM6 TRIM5 TRIM4 Figure 8-13. ICG Trim Register (ICGTR) Internal Clock Generator Module (ICG Bit 0 TRIM3 TRIM2 TRIM1 TRIM0 MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 143

... DDIV is controlled by the digital loop filter. The range of valid values for DDIV is from $0 to $9. Values of $A–$F are interpreted the same as $9. Since the DCO is active during reset, reset has no effect on DSTG and the value may vary. MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 144

... DCO is active during reset, reset has no effect on DSTG and the value may vary. Advance Information 144 Bit DSTG6 DSTG5 DSTG4 Unaffected by reset = Unimplemented Figure 8-15. ICG DCO Stage Register (ICGDSR) Internal Clock Generator Module (ICG Bit 0 DSTG3 DSTG2 DSTG1 DSTG0 MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 145

... Advance Information — MC68HC908RK2 Section 9. Configuration Register (CONFIG) 9.1 Contents 9.2 9.3 9.2 Introduction This section describes the configuration register (CONFIG). The configuration register enables or disables these options: • • • • • 9.3 Functional Description The CONFIG register is used in the initialization of various options and can be written once after each reset. The register is set to the documented value during reset ...

Page 146

... LVI disabled during stop mode Section 12. Low-Voltage Inhibit 1 = LVI module resets enabled 0 = LVI module resets disabled (LVI).) 1 = LVI module power enabled 0 = LVI module power disabled Configuration Register (CONFIG Bit 0 COPRS SSREC STOP COPD (ICG).) (LVI).) Section 12. Low-Voltage MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 147

... LVI is not protecting the MCU. STOP — STOP Instruction Enable Bit STOP enables the STOP instruction. COPD — COP Disable Bit COPD disables the COP module. (See Operating Properly Module MC68HC908RK2 Rev. 4.0 — MOTOROLA 1 = COP timeout period = COP timeout period = 2 ...

Page 148

... Configuration Register (CONFIG) Advance Information 148 Configuration Register (CONFIG) MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 149

... Advance Information — MC68HC908RK2 Section 10. Monitor Read-Only Memory (MON) 10.1 Contents 10.2 10.3 10.4 10.4.1 10.4.2 10.4.3 10.4.4 10.4.5 10.4.6 10.4.7 10.2 Introduction This section describes the monitor read-only memory (MON). The MON allows complete testing of the MCU through a single-wire interface with a host computer. MC68HC908RK2 Rev. 4.0 — MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Monitor Mode Entry ...

Page 150

... RS-232 interface. While simple monitor commands can access any memory address, the MC68HC908RK2 has a FLASH security feature to prevent external viewing of the contents of FLASH. Proper procedures must be followed to verify FLASH content. Access to the FLASH is denied to unauthorized ...

Page 151

... MC145407 + DB- MC68HC908RK2 Rev. 4.0 — MOTOROLA MC74HC125 Figure 10-1. Monitor Mode Circuit Monitor Read-Only Memory (MON) Monitor Read-Only Memory (MON) Functional Description V DD 68HC908RK2 10 k RST 0 ...

Page 152

... Applying a logic 0 and then a logic 1 to the RST pin Security). After the security bytes, the MCU sends a break Section 6. System Integration for more information on modes of operation.) The ICG Monitor Read-Only Memory (MON) Bus (2) Frequency CGMOUT ------------------------- - 2 2 and 16.3 Absolute Maximum HI Specifications) is applied to either is applied to the HI MC68HC908RK2 Rev. 4.0 — MOTOROLA (see ...

Page 153

... BREAK BIT 0 BIT Notes Echo delay (2 bit times Data return delay (2 bit times Wait 1 bit time before sending next byte. Figure 10-3. Sample Monitor Waveforms MC68HC908RK2 Rev. 4.0 — MOTOROLA is a summary of the differences between user mode and Table 10-2. Mode Differences Reset COP ...

Page 154

... ROM immediately echoes each READ ADDR. HIGH ADDR. HIGH ADDR. LOW Figure 10-4. Read Transaction 2-STOP-BIT DELAY BEFORE ZERO ECHO Figure 10-5. Break Transaction Monitor Read-Only Memory (MON) ADDR. LOW DATA 1 2 RESULT Figure 10-5 MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 155

... Command Sequence SENT TO MONITOR READ ECHO Notes Echo delay (2 bit times Data return delay (2 bit times Wait 1 bit time before sending next byte. MC68HC908RK2 Rev. 4.0 — MOTOROLA READ, read memory WRITE, write memory IREAD, indexed read IWRITE, indexed write READSP, read stack pointer ...

Page 156

... MONITOR ECHO Notes Echo delay (2 bit times Data return delay (2 bit times) Advance Information 156 ADDR. HIGH ADDR. HIGH ADDR. LOW IREAD IREAD DATA 1 2 Monitor Read-Only Memory (MON) ADDR. LOW DATA DATA 2 1 DATA 2 RESULT MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 157

... Returns stack pointer plus one in high byte:low byte order. The plus one is due to Data Returned the use of the TSX instruction. Opcode $0C Command Sequence SENT TO MONITOR ECHO Notes Echo delay (2 bit times) MC68HC908RK2 Rev. 4.0 — MOTOROLA IWRITE IWRITE 1 2 ECHO 2 = Wait 1 bit time before sending next byte. ...

Page 158

... During monitor mode entry, the MCU waits after the power-on reset for the host to send the eight security bytes on pin PA0. Advance Information 158 SENT TO MONITOR RUN RUN 1 ECHO Note 1 = Echo delay (2 bit times) applied to IRQ1, the MCU bus clock is HI Monitor Read-Only Memory (MON) MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 159

... FLASH locations returns undefined data, and trying to execute code from FLASH causes an illegal address reset. After the host fails to bypass security, any reset other than a power-on reset causes an endless loop of illegal address resets. MC68HC908RK2 Rev. 4.0 — MOTOROLA 24 CGMXCLK CYCLES will guarantee that the MCU bus is driven by the external clock ...

Page 160

... After receiving the eight security bytes from the host, the MCU transmits a break character signalling that it is ready to receive a command. NOTE: The MCU does not transmit a break character until after the host sends the eight security bytes. Advance Information 160 Monitor Read-Only Memory (MON) MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 161

... Advance Information — MC68HC908RK2 Section 11. Computer Operating Properly Module (COP) 11.1 Contents 11.2 11.3 11.4 11.4.1 11.4.2 11.4.3 11.4.4 11.4.5 11.4.6 11.4.7 11.4.8 11.5 11.6 11.7 11.8 11.8.1 11.8.2 11.9 MC68HC908RK2 Rev. 4.0 — MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 CGMXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Reset Vector Fetch 164 COPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 COPRS ...

Page 162

... COPD FROM CONFIG COPRS FROM CONFIG Advance Information 162 Computer Operating Properly Module (COP) 12-BIT COP PRESCALER CGMXCLK COPCTL WRITE 6-BIT COP COUNTER RESET CLEAR COP COPCTL WRITE COUNTER Figure 11-1. COP Block Diagram RESET RESET STATUS REGISTER MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 163

... I/O Signals The following paragraphs describe the signals shown in 11.4.1 CGMXCLK CGMXCLK is the oscillator output signal. See Circuit 11.4.2 STOP Instruction The STOP instruction clears the COP prescaler. MC68HC908RK2 Rev. 4.0 — MOTOROLA . During the break state for a description of CGMXCLK. Computer Operating Properly Module (COP) ...

Page 164

... The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register. (See (CONFIG)). Advance Information 164 Computer Operating Properly Module (COP) Register), clears the COP counter and clears stages 12 Section 9. Configuration Register Section 9. Configuration Register 11.5 COP MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 165

... The WAIT and STOP instructions put the MCU in low power- consumption standby modes. 11.8.1 Wait Mode The COP remains active in wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter in a CPU interrupt routine. MC68HC908RK2 Rev. 4.0 — MOTOROLA $FFFF ...

Page 166

... COP with a STOP instruction, disable the STOP instruction by clearing the STOP bit. 11.9 COP Module During Break Interrupts The COP is disabled during a break interrupt when V RST pin. Advance Information 166 Computer Operating Properly Module (COP) Section 9. Configuration Register MC68HC908RK2 (CONFIG)) is present on the HI Rev. 4.0 — MOTOROLA ...

Page 167

... Advance Information — MC68HC908RK2 12.1 Contents 12.2 12.3 12.4 12.4.1 12.4.2 12.5 12.6 12.7 12.7.1 12.7.2 12.2 Introduction The low-voltage inhibit (LVI) module monitors the voltage on the V and will set a low voltage sense bit when V sense voltage. The LVI will force a reset when the V the LVI trip voltage. MC68HC908RK2 Rev. 4.0 — MOTOROLA Section 12. Low-Voltage Inhibit (LVI) Introduction ...

Page 168

... LVS LVS Figure 12-1. LVI Module Block Diagram Low-Voltage Inhibit (LVI) falls below the V threshold. DD LVR falls below V DD LVS STOP INSTRUCTION LVI STOP BIT IN CONFIGURATION REGISTER RESET V LVITRIP DD DIGITAL FILTER LOWV LOWV FLAG MC68HC908RK2 Rev. 4.0 — MOTOROLA , ...

Page 169

... CGMXCLK delay must be greater than the LVI turn on time to avoid a period in startup where the LVI is not protecting the MCU. NOTE: The LVI is enabled automatically after reset or stop recovery, if the LVISTOP of the CONFIG register is set. (See Register MC68HC908RK2 Rev. 4.0 — MOTOROLA pin level is digitally filtered to reduce false dead battery DD ...

Page 170

... LOWV Unimplemented Figure 12-2. LVI Status Register (LVISR) voltage for CGMXCLK cycles. Reset clears the LVIOUT threshold. LVS Low-Voltage Inhibit (LVI) and V LVR LVS Bit voltage falls below the DD DD MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 171

... The LVI module remains active in wait mode. The LVI module can generate a reset 12.7.2 Stop Mode The LVI can be enabled or disabled in stop mode by setting the LVISTOP bit in the CONFIG register. (See Register NOTE: To minimize STOP I MC68HC908RK2 Rev. 4.0 — MOTOROLA voltage below the V DD (CONFIG).) disable the LVI in stop mode. ...

Page 172

... Low-Voltage Inhibit (LVI) Advance Information 172 Low-Voltage Inhibit (LVI) MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 173

... Advance Information — MC68HC908RK2 13.1 Contents 13.2 13.3 13.3.1 13.3.2 13.4 13.4.1 13.4.2 13.2 Introduction Fourteen bidirectional input/output (I/O) pins form two parallel ports in the 20-pin SSOP/SOIC package. All I/O pins are programmable as inputs or outputs. Port A bits PTA6–PTA1 have keyboard wakeup interrupts and internal pullup resistors. NOTE: Connect any unused I/O pins to an appropriate logic level, either V ...

Page 174

... Unaffected by reset DDRA7 DDRA6 DDRA5 DDRA4 MCLKEN DDRB5 DDRB4 Unimplemented Input/Output (I/O) Ports Bit 0 PTA3 PTA2 PTA1 PTA0 PTB3 PTB2 PTB1 PTB0 DDRA3 DDRA2 DDRA1 DDRA0 DDRB3 DDRB2 DDRB1 DDRB0 MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 175

... Keyboard/External Interrupt Module NOTE: The enabling of a keyboard interrupt pin will overide the corresponding definition of the pin in the data direction register. However, the data direction register bit must be a logic 0 for software to read the pin. MC68HC908RK2 Rev. 4.0 — MOTOROLA $0000 Bit 7 ...

Page 176

... DDRA7 DDRA6 DDRA5 DDRA4 Figure 13-3. Data Direction Register A (DDRA Corresponding port A pin configured as output 0 = Corresponding port A pin configured as input shows the port A I/O logic. Input/Output (I/O) Ports Bit 0 DDRA3 DDRA2 DDRA1 DDRA0 Table 13-1 summarizes MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 177

... NOTE: Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard interrupt pin input, overriding the data direction register. However, the data direction register bit must be a logic 0 for software to read the pin. MC68HC908RK2 Rev. 4.0 — MOTOROLA READ DDRA ($0004) ...

Page 178

... Bit PTB5 PTB4 Unaffected by reset TCH1 = Unimplemented Figure 13-5. Port B Data Register (PTB) Section 15. Timer Interface Module Section 15. Timer Interface Module Input/Output (I/O) Ports Bit 0 PTB3 PTB2 PTB1 PTB0 TCLK TCH0 MCLK (TIM). (TIM). MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 179

... This read/write bit enables MCLK output signal on PTB0. If MCLK is enabled, PTB0 is under the control of MCLKEN. Reset clears this bit. DDRB[5:0] — Data Direction Register B Bits These read/write bits control port B data direction. Reset clears DDRB[5:0], configuring all port B pins as inputs. MC68HC908RK2 Rev. 4.0 — MOTOROLA $0005 Bit 7 ...

Page 180

... PTBx READ PTB ($0001) Figure 13-7. Port B I/O Circuit Table 13-2. Port B Pin Functions Accesses PTB I/O Pin to DDRB Bit Mode Read/Write X Input, Hi-Z DDRB[5:0] X Output DDRB[5:0] Input/Output (I/O) Ports Table 13-2 summarizes Accesses to PTB Read Write DDRB[7] Pin PTB[5:0] DDRB[7] PTB[5:0] PTB[5:0] MC68HC908RK2 Rev. 4.0 — MOTOROLA PTBx (1) ...

Page 181

... Advance Information — MC68HC908RK2 Section 14. Keyboard/External Interrupt Module (KBI) 14.1 Contents 14.2 14.3 14.4 14.4.1 14.4.2 14.4.3 14.4.4 14.4.5 14.5 14.5.1 14.5.2 14.6 14.6.1 14.6.2 14.2 Introduction This section describes the maskable external interrupt (IRQ1) input and six independently maskable keyboard wakeup interrupt pins. MC68HC908RK2 Rev. 4.0 — MOTOROLA Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 IRQ1 Pin ...

Page 182

... Internal pullup resistor Hysteresis buffer Programmable edge-only or edge- and level-interrupt sensitivity Automatic interrupt acknowledge Figure 14-1 shows the structure of the external (IRQ1) Figure 14-4 for a summary of the interrupt and keyboard Keyboard/External Interrupt Module (KBI) shows the structure of the MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 183

... Control Register $001A Write: (INTKBSCR) See page 191. Reset: Read: Keyboard Interrupt Enable Register $001B Write: (INTKBIER) See page 193. Reset: Figure 14-2. IRQ and Keyboard I/O Register Summary MC68HC908RK2 Rev. 4.0 — MOTOROLA V DD CLR IRQ1 LATCH IMASKI MODEI Figure 14-1. IRQ Block Diagram ...

Page 184

... Writing a logic 1 to the ACKI bit clears the IRQ1 latch. Writing a logic 1 to the ACKK bit clears the keyboard interrupt latch. Reset — A reset automatically clears both interrupt latches. Vector fetch or software clear Return of the interrupt pin to logic 1 Keyboard/External Interrupt Module (KBI) MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 185

... NOTE: The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including external interrupt requests. (See MC68HC908RK2 Rev. 4.0 — MOTOROLA Figure 14-3.) FROM RESET YES I BIT SET? NO YES INTERRUPT? NO FETCH NEXT INSTRUCTION SWI YES INSTRUCTION? NO RTI YES INSTRUCTION? NO Figure 14-3. IRQ Interrupt Flowchart ...

Page 186

... If the IRQ1 mask bit, IMASKI, is clear, the CPU loads the program counter with the vector address at locations $FFFA and $FFFB. Return of the IRQ1 pin to logic 1 — As long as the IRQ1 pin is at logic 0, the IRQ1 latch remains set. Keyboard/External Interrupt Module (KBI) MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 187

... An IRQ1/keyboard interrupt is latched when one or more keyboard pins goes low after all were high. The MODEK bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. • • MC68HC908RK2 Rev. 4.0 — MOTOROLA Register.) If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low ...

Page 188

... Return of all enabled keyboard interrupt pins to logic 1. As long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. Keyboard/External Interrupt Module (KBI) INTERNAL BUS VECTOR FETCH DECODER KEYF SYNCHRONIZER KEYBOARD INTERRUPT REQUEST IRQ1 INTERRUPT IRQ1/KEYBOARD REQUEST INTERRUPT REQUEST MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 189

... Mask keyboard interrupts by setting the IMASKK bit in the 2. Enable the KBI pins by setting the appropriate KBIEx bits in the 3. Write to the ACKK bit in the keyboard status and control register 4. Clear the IMASKK bit. MC68HC908RK2 Rev. 4.0 — MOTOROLA keyboard status and control register. ...

Page 190

... IMASKI or IMASKK bit in the IRQ and keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode. Advance Information 190 DDRA bits in data direction register A. keyboard interrupt enable register. Keyboard/External Interrupt Module (KBI) MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 191

... Write: Reset: Figure 14-5. IRQ and Keyboard Status and Control Register IRQ1F — IRQ1 Flag Bit This read-only status bit is high when the IRQ1 interrupt is pending. MC68HC908RK2 Rev. 4.0 — MOTOROLA IRQ and keyboard status and control register (INTKBSCR) Keyboard interrupt enable register (KBIER) ...

Page 192

... Keyboard interrupt pending keyboard interrupt pending 1 = Keyboard interrupt requests masked 0 = Keyboard interrupt requests not masked 1 = Keyboard interrupt requests on falling edges and low levels 0 = Keyboard interrupt requests on falling edges only Keyboard/External Interrupt Module (KBI) MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 193

... Reset clears the keyboard interrupt enable register. NOTE: Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard interrupt pin input, overriding the data direction register. However, the data direction register bit must be a logic 0 for software to read the pin. MC68HC908RK2 Rev. 4.0 — MOTOROLA Bit 7 6 ...

Page 194

... Keyboard/External Interrupt Module (KBI) Advance Information 194 Keyboard/External Interrupt Module (KBI) MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 195

... Advance Information — MC68HC908RK2 15.1 Contents 15.2 15.3 15.4 15.5 15.5.1 15.5.2 15.5.3 15.5.4 15.5.5 15.5.6 15.5.7 15.5.8 15.5.9 15.6 15.6.1 15.6.2 15.6.3 15.7 15.8 15.8.1 15.8.2 15.9 15.9.1 15.9.2 15.9.3 15.9.4 15.9.5 MC68HC908RK2 Rev. 4.0 — MOTOROLA Section 15. Timer Interface Module (TIM) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . .199 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .200 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . 201 Pulse-Width Modulation (PWM) ...

Page 196

... Free-running or modulo up-count operation Toggle any channel pin on overflow TIM counter stop and reset bits 15-1. Table 15-1. Pin Name Conventions TIM Generic TCH0 Pin Names: Full TIM PTB2/TCH0 Pin Names: Timer Interface Module (TIM) 2 maximum) TCH1 TCLK PTB4/TCH1 PTB3/TCLK MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 197

... COUNTER 16-BIT COMPARATOR TMODH:TMODL CHANNEL 0 16-BIT COMPARATOR TCH0H:TCH0L 16-BIT LATCH CHANNEL 1 16-BIT COMPARATOR TCH1H:TCH1L 16-BIT LATCH MC68HC908RK2 Rev. 4.0 — MOTOROLA shows the structure of the TIM. The central component of Figure 15-2 for a summary of the TIM I/O registers. PRESCALER SELECT PS2 PS1 PS0 ELS0B ...

Page 198

... Bit Bit Bit Bit ELS0B ELS0A TOV0 CH0MAX Bit Bit 0 ELS1B ELS1A TOV1 CH1MAX MC68HC908RK2 Rev. 4.0 — MOTOROLA ...

Page 199

... With the output compare function, the TIM can generate a periodic pulse with a programmable polarity, duration, and frequency. When the counter reaches the value in the registers of an output compare channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU interrupt requests. MC68HC908RK2 Rev. 4.0 — MOTOROLA Bit 7 ...

Page 200

... Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. Timer Interface Module (TIM) Compare. The pulses are MC68HC908RK2 Rev. 4.0 — MOTOROLA ...