mc68hc908rk2 Freescale Semiconductor, Inc, mc68hc908rk2 Datasheet - Page 84

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mc68hc908rk2

Manufacturer Part Number
mc68hc908rk2
Description
Hcmos Microcontroller Unit
Manufacturer
Freescale Semiconductor, Inc
Datasheet
System Integration Module (SIM)
6.3.3 Clocks in Stop Mode and Wait Mode
6.4 Reset and System Initialization
Advance Information
84
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows
CGMXCLK to clock the SIM counter. The CPU and peripheral clocks do
not become active until after the stop delay timeout. This timeout is
selectable as 4096 or 32 CGMXCLK cycles. (See
In wait mode, the CPU clocks are inactive. Refer to the wait mode
subsection of each module to see if the module is active or inactive in
wait mode. Some modules can be programmed to be active in wait
mode.
The MCU has these reset sources:
All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in
monitor mode) and assert the internal reset signal (IRST). IRST causes
all registers to be returned to their default values and all modules to be
returned to their reset states.
An internal reset clears the SIM counter (see
external reset does not. Each of the resets sets a corresponding bit in
the SIM reset status register (SRSR). (See
Power-on reset module (POR)
External Reset Pin (RST)
Computer operating properly module (COP)
Low-voltage inhibit module (LVI)
Illegal opcode
Illegal address
System Integration Module (SIM)
6.8 SIM
6.5 SIM
MC68HC908RK2
6.7.2 Stop
Registers.)
Counter), but an
MOTOROLA
Mode.)
Rev. 4.0

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