mc68hc908rk2 Freescale Semiconductor, Inc, mc68hc908rk2 Datasheet - Page 97

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mc68hc908rk2

Manufacturer Part Number
mc68hc908rk2
Description
Hcmos Microcontroller Unit
Manufacturer
Freescale Semiconductor, Inc
Datasheet
6.8 SIM Registers
6.8.1 SIM Break Status Register
;This code works if the H register has been pushed onto the stack in the break
;service routine software. This code should be executed at the end of the
;break service routine software.
HIBYTE
LOBYTE
;
DOLO
RETURN
MC68HC908RK2
MOTOROLA
EQU
EQU
If not SBSW, do RTI
BRCLR
TST
BNE
DEC
DEC
PULH
RTI
Rev. 4.0
5
6
SBSW, SBSR, RETURN
LOBYTE,SP
DOLO
HIBYTE,SP
LOBYTE,SP
Address:
The SIM has three memory mapped registers:
The SIM break status register (SBSR) contains a flag to indicate that a
break caused an exit from stop or wait mode.
SBSW — SIM Break Stop/Wait Bit
Reset:
Read:
Write:
This status bit is useful in applications requiring a return to wait or stop
mode after exiting from a break interrupt. Clear SBSW by writing a
logic 0 to it. Reset clears SBSW.
SBSW can be read within the break state SWI routine. The user can
modify the return address on the stack by subtracting one from it.
(See code example.) Writing 0 to the SBSW bit clears it.
1 = Stop mode or wait mode was exited by break interrupt.
0 = Stop mode or wait mode was not exited by break interrupt.
SIM break status register, SBSR
SIM reset status register, SRSR
SIM break flag control register, SBFCR
$FE00
Bit 7
R
R
Figure 6-17. SIM Break Status Register (SBSR)
System Integration Module (SIM)
= Reserved
6
R
;See if wait mode or stop mode was exited
;by break.
;If RETURNLO is not zero,
;then just decrement low byte.
;Else deal with high byte, too.
;Point to WAIT/STOP opcode.
;Restore H register.
R
5
R
4
Note: Writing a logic 0 clears SBSW.
R
3
System Integration Module (SIM)
R
2
Advance Information
See Note
SBSW
1
0
SIM Registers
Bit 0
R
97

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