mc68hc908rk2 Freescale Semiconductor, Inc, mc68hc908rk2 Datasheet - Page 141

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mc68hc908rk2

Manufacturer Part Number
mc68hc908rk2
Description
Hcmos Microcontroller Unit
Manufacturer
Freescale Semiconductor, Inc
Datasheet
8.8.2 ICG Multiplier Register
MC68HC908RK2
MOTOROLA
Rev. 4.0
Address: $0037
Reset:
Read:
Write:
ECGON — External Clock Generator On Bit
ECGS — External Clock Generator Stable Bit
N6–N0 — ICG Multiplier Factor Bits
This read/write bit enables the external clock generator. ECGON can
be cleared when the CS and CMON bits have been clear for at least
one bus cycle. ECGON is forced set when the CMON bit or the CS bit
is set. ECGON is forced clear during reset.
This read-only bit indicates when at least 4096 external clock (ECLK)
cycles have elapsed since the external clock generator was enabled.
This is not an assurance of the stability of ECLK but is meant to
provide a start-up delay. This bit is forced clear when the clock
monitor determines ECLK is inactive, when ECGON is clear, or during
reset.
These read/write bits change the multiplier used by the internal clock
generator. The internal clock (ICLK) will be (307.2 kHz 25
percent) * N. A value of $00 in this register is interpreted the same as
a value of $01. This register cannot be written when the CMON bit is
set. Reset sets this factor to $15 (decimal 21) for default frequency of
6.45 MHz 25 percent (1.613 MHz 25 percent bus).
1 = External clock generator enabled
0 = External clock generator disabled
1 = 4096 ECLK cycles have elapsed since ECGON was set.
0 = External cock is unstable, inactive, or disabled.
Bit 7
R
R
0
Internal Clock Generator Module (ICG)
Figure 8-12. ICG Multiplier Register (ICGMR)
= Reserved
N6
6
0
N5
5
0
N4
4
1
Internal Clock Generator Module (ICG)
N3
3
0
N2
2
1
Advance Information
N1
1
0
I/O Registers
Bit 0
N0
1
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