mc68hc908sr12 Freescale Semiconductor, Inc, mc68hc908sr12 Datasheet - Page 150

• Manufacturer Part Number: mc68hc908sr12
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

System Integration Module (SIM)
9.4.2.3 Illegal Opcode Reset
9.4.2.4 Illegal Address Reset
9.4.2.5 Low-Voltage Inhibit (LVI) Reset
9.4.2.6 Monitor Mode Entry Module Reset
Data Sheet
150
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the SIM reset status register
(SRSR) and causes a reset.
If the stop enable bit, STOP, in the mask option register is logic 0, the
SIM treats the STOP instruction as an illegal opcode and causes an
illegal opcode reset. The SIM actively pulls down the RST pin for all
internal reset sources.
An opcode fetch from an unmapped address generates an illegal
address reset. The SIM verifies that the CPU is fetching an opcode prior
to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not
generate a reset. The SIM actively pulls down the RST pin for all internal
reset sources.
The low-voltage inhibit module (LVI) asserts its output to the SIM when
the V
status register (SRSR) is set, and the external reset pin (RST) is held low
while the SIM counter counts out 4096 + 32 ICLK cycles. Thirty-two ICLK
cycles later, the CPU is released from reset to allow the reset vector
sequence to occur. The SIM actively pulls down the RST pin for all
internal reset sources.
The monitor mode entry module reset asserts its output to the SIM when
monitor mode is entered in the condition where the reset vectors are
blank ($FF). (See
gets asserted, an internal reset occurs. The SIM actively pulls down the
RST pin for all internal reset sources.
DD
voltage falls to the LVI
System Integration Module (SIM)
Section 10. Monitor ROM
TRIPF
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
voltage. The LVI bit in the SIM reset
(MON).) When MODRST
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