mc68hc908sr12 Freescale Semiconductor, Inc, mc68hc908sr12 Datasheet - Page 244

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mc68hc908sr12

Manufacturer Part Number
mc68hc908sr12
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Analog-to-Digital Converter (ADC)
15.8.2 ADC Clock Control Register
Data Sheet
244
Address:
The ADC clock control register (ADICLK) selects the clock frequency for
the ADC.
ADIV[2:0] — ADC Clock Prescaler Bits
ADICLK — ADC Input Clock Select Bit
Reset:
Read:
Write:
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide
ratio used by the ADC to generate the internal ADC clock.
Table 15-2
should be set to between 500kHz and 2MHz.
ADICLK selects either bus clock or CGMXCLK as the input clock
source to generate the internal ADC clock. Reset selects CGMXCLK
as the ADC clock source.
Figure 15-4. ADC Clock Control Register (ADICLK)
ADIV2
$0058
ADIV2
X = don’t care
Analog-to-Digital Converter (ADC)
0
0
0
0
0
1
shows the available clock configurations. The ADC clock
= Unimplemented
ADIV1
Table 15-2. ADC Clock Divide Ratio
0
ADIV1
X
0
0
1
1
ADIV0
0
ADIV0
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
X
0
1
0
1
ADICLK
0
MODE1
ADC input clock ÷ 1
ADC input clock ÷ 2
ADC input clock ÷ 4
ADC input clock ÷ 8
ADC input clock ÷ 16
R
0
ADC Clock Rate
= Reserved
MODE0
Freescale Semiconductor
1
0
0
R
0
0

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