mc68hc908bd48 Freescale Semiconductor, Inc, mc68hc908bd48 Datasheet - Page 97

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mc68hc908bd48

Manufacturer Part Number
mc68hc908bd48
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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7.5.2 SIM Counter During Stop Mode Recovery
7.5.3 SIM Counter and Reset States
7.6 Exception Control
MC68HC908BD48
Freescale Semiconductor
Rev. 2.1
The SIM counter also is used for stop mode recovery. The STOP
instruction clears the SIM counter. After an interrupt, break, or reset, the
SIM senses the state of the short stop recovery bit, SSREC, in the
configure register 1 (CONFIG1). If the SSREC bit is a logic one, then the
stop recovery is reduced from the normal delay of 4096 OSCXCLK
cycles down to 32 OSCXCLK cycles. This is ideal for applications using
canned oscillators that do not require long start-up times from stop
mode. External crystal applications should use the full stop recovery
time, that is, with SSREC cleared.
External reset has no effect on the SIM counter
The SIM counter is free-running after all reset states
Resets from Internal Sources
recovery sequences).
Normally, sequential program execution can be changed in three
different ways:
Interrupts
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
Reset
Break interrupts
System Integration Module (SIM)
for counter control and internal reset
System Integration Module (SIM)
(see 7.7.2 Stop
(see 7.4.2 Active
Data Sheet
Mode).
97

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