mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 320

• Manufacturer Part Number: mc68hc916y3
• Description: Mc68hc16y3 16 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

14.5.4 Programmable Time Accumulator (PTA)
14.5.5 Multichannel Pulse-Width Modulation (MCPWM)
14.5.6 Fast Quadrature Decode (FQD)
14-12
MOTOROLA
PTA accumulates a 32-bit sum of the total high time, low time, or period of an input
signal over a programmable number of periods or pulses. The accumulation can start
on a rising or falling edge. After the specified number of periods or pulses, PTA
generates an interrupt request and optionally generates links to other channels.
From one to 255 period measurements can be made and summed with the previous
measurement(s) before the TPU2 interrupts the CPU16, providing instantaneous or
average frequency measurement capability, and the latest complete accumulation
(over the programmed number of periods).
Refer to TPU programming note Programmable Time Accumulator (PTA) TPU Func-
tion (TPUPN06/D) for more information.
MCPWM generates pulse-width modulated outputs with full 0% to 100% duty cycle
range independent of other TPU2 activity. This capability requires two TPU2 channels
plus an external gate for one PWM channel. (A simple one-channel PWM capability is
supported by the QOM function.)
Multiple PWMs generated by MCPWM have two types of high time alignment: edge
aligned and center aligned. Edge aligned mode uses n + 1 TPU2 channels for n
PWMs; center aligned mode uses 2n + 1 channels. Center aligned mode allows a
user-defined “dead time” to be specified so that two PWMs can be used to drive an H-
bridge without destructive current spikes. This feature is important for motor control
applications.
Refer to TPU programming note Multichannel Pulse-Width Modulation (MCPWM)
TPU Function (TPUPN05/D) for more information.
FQD is a position feedback function for motor control. It decodes the two signals from
a slotted encoder to provide the CPU16 with a 16-bit free running position counter.
FQD incorporates a “speed switch” which disables one of the channels at high speed,
allowing faster signals to be decoded. A time stamp is provided on every counter up-
date to allow position interpolation and better velocity determination at low speed or
when low resolution encoders are used. The third index channel provided by some en-
coders is handled by the NITC function.
Refer to TPU programming note Fast Quadrature Decode (FQD) TPU Function
(TPUPN02/D) for more information.
Freescale Semiconductor, Inc.
For More Information On This Product,
TIME PROCESSOR UNIT 2
Go to: www.freescale.com
MC68HC16Y3/916Y3
USER’S MANUAL