mc68hc05ct4fn Freescale Semiconductor, Inc, mc68hc05ct4fn Datasheet - Page 57

• Manufacturer Part Number: mc68hc05ct4fn
• Description: Mc68hc05 Family Of Microcontrollers Mcus
• Manufacturer: Freescale Semiconductor, Inc

7.6 Port D
7.7 Input/Output Port Pin Programming
MC68HC05CT4
—
Rev. 2.0
Port D is a 7-bit bidirectional port. Two of its pins are shared with the SSI
subsystem, four are shared with the comparators, and one is shared with
the timer. During reset, all seven bits become valid input ports because
all special function output drivers associated with the timer and SSI
subsystems are disabled.
Port pins may be programmed as inputs or outputs under software
control. The direction of the pins is determined by the state of the
corresponding bit in the port data direction register (DDR). Each I/O port
has an associated DDR. Any I/O port pin is configured as an output if its
corresponding DDR bit is set to a logic one. A pin is configured as an
input if its corresponding DDR bit is cleared to a logic 0.
At power-on or reset, all DDRs are cleared, which configures all pins as
inputs. The data direction registers are capable of being written to or
read by the processor. During the programmed output state, a read of
the data register actually reads the value of the output data latch and not
the I/O pin.
Refer to
Freescale Semiconductor, Inc.
R/W
0
0
1
1
For More Information On This Product,
Table 7-1
Go to: www.freescale.com
Parallel Input/Output (I/O)
DDR
0
1
0
1
and to
Table 7-1. I/O PIn Functions
The I/O pin is in input mode. Data is written into the output
Data is written into the output data latch and output to the
The state of the I/O pin is read.
The I/O pin is in an output mode. The output data latch is
data latch.
I/O pin.
read.
Figure 7-2
for additional information.
I/O Pin Functions
General Release Specification
Parallel Input/Output (I/O)
Port D