mc68hc05ct4fn Freescale Semiconductor, Inc, mc68hc05ct4fn Datasheet - Page 74

• Manufacturer Part Number: mc68hc05ct4fn
• Description: Mc68hc05 Family Of Microcontrollers Mcus
• Manufacturer: Freescale Semiconductor, Inc

Synchronous Serial Interface (SSI)
General Release Specification
NOTE:
CPOL — Clock Polarity
If the SSI is used as a slave, the SCK input pin must be active before
enabling the SSI. For example, if CPOL = 0, SCK must be low; if
CPOL = 1, SCK must be high.
T/R — Transmit/Receive
SR1 and SR0 — SSI Rate
When cleared, this bit configures the SSI to the slave mode and
aborts any transmission in progress. Transfers are initiated by an
external master, which should supply the clock to the SCK pin.
The clock polarity bit controls the state of the SCK pin between
transmissions.
When this bit is set, pin SCK is high between transmissions.
When this bit is cleared, pin SCK is low between transmissions.
In both cases the data is latched on the rising edge of SCK for serial
input and is valid on the rising edge of SCK for serial output. A reset
sets this bit.
This bit must be set to allow data to be driven on the SDIO pin
(transmitting). It must be cleared to disable the SDIO drivers when
receiving data. It is cleared by a reset.
These bits determine the frequency of SCK when in master mode
(MSTR = 1). They have no effect in slave mode (MSTR = 0).
Freescale Semiconductor, Inc.
For More Information On This Product,
Synchronous Serial Interface (SSI)
Go to: www.freescale.com
SR1 and SR0
00
01
10
11
Table 9-1. SSI Rates
SCK Rates (Hz) at f
128 kHz
256 kHz
32 kHz
64 kHz
osc
Frequency
MC68HC05CT4
—
Rev. 2.0