mc68hc05ct4fn Freescale Semiconductor, Inc, mc68hc05ct4fn Datasheet - Page 72

• Manufacturer Part Number: mc68hc05ct4fn
• Description: Mc68hc05 Family Of Microcontrollers Mcus
• Manufacturer: Freescale Semiconductor, Inc

Synchronous Serial Interface (SSI)
9.4 SSI Registers
9.4.1 SSI Control Register
General Release Specification
If (CPOL = 0), the first data bit will be driven out to the SDIO pin before
the first rising edge of SCK. Subsequent falling edges of SCK will shift
the remaining data bits out.
When receiving data in master mode, the T/R bit must be low and data
must be written to the data register to initiate clock generation.
When transmitting data in master mode, the T/R bit must be high.
When receiving data in slave mode, T/R bit must be low and the clock
and data must be supplied by external device.
When transmitting data in slave mode, T/R bit must be high, and data
must be written to the data register before the SSI is enabled to ensure
that proper data is transferred.
The SSI has three registers: control, status, and data.
This register is located at address $001E and contains seven bits. A
reset clears all of these bits, except bit 3 which is set. Writes to this
register during a transfer should be avoided, with the exception of
clearing the SE bit to disable the SSI.
In addition, the clock polarity, rate, data format and master/slave
selection should not be changed while the SSI is enabled (SE = 1) or
(CPOL = 1)
(CPOL = 0)
Freescale Semiconductor, Inc.
SDIO
SCK
SCK
For More Information On This Product,
SE
Synchronous Serial Interface (SSI)
Go to: www.freescale.com
Figure 9-2. Serial I/O Port Timing
BIT 1
BIT 2
BIT 3
MC68HC05CT4
BIT 7
BIT 8
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Rev. 2.0