mc68hc11d0 Freescale Semiconductor, Inc, mc68hc11d0 Datasheet - Page 55

• Manufacturer Part Number: mc68hc11d0
• Description: Mc68hc11d0 Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

5.4.4 Software Interrupt
5.4.5 Maskable Interrupts
5.4.6 Reset and Interrupt Processing
TECHNICAL DATA
The stacked return address can be used as a pointer to the illegal opcode so the illegal
opcode service routine can evaluate the offending opcode.
SWI is an instruction, and thus cannot be interrupted until complete. SWI is not inhib-
ited by the global mask bits in the CCR. Because execution of SWI sets the I mask bit,
once an SWI interrupt begins, other interrupts are inhibited until SWI is complete, or
until user software clears the I bit in the CCR.
The maskable interrupt structure of the MCU can be extended to include additional ex-
ternal interrupt sources through the IRQ pin. The default configuration of this pin is a
low-level sensitive wired-OR network. When an event triggers an interrupt, a software
accessible interrupt flag is set. When enabled, this flag causes a constant request for
interrupt service. After the flag is cleared, the service request is released.
Figure 5-1 and Figure 5-1 illustrate the reset and interrupt process. Figure 5-1 illus-
trates how the CPU begins from a reset and how interrupt detection relates to normal
opcode fetches. Figure 5-1 is an expansion of a block in Figure 5-1 and illustrates in-
terrupt priorities. Figure 5-2 shows the resolution of interrupt sources within the SCI
subsystem.
Freescale Semiconductor, Inc.
For More Information On This Product,
RESETS AND INTERRUPTS
Go to: www.freescale.com
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