mc68hc11d0 Freescale Semiconductor, Inc, mc68hc11d0 Datasheet - Page 84

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mc68hc11d0

Manufacturer Part Number
mc68hc11d0
Description
Mc68hc11d0 Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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SPCR — Serial Peripheral Control Register
8.5.1 Serial Peripheral Control
SPIE — Serial Peripheral Interrupt Enable
SPE — Serial Peripheral System Enable
DWOM — Port D Wired-OR Mode
MSTR — Master Mode Select
CPOL — Clock Polarity
CPHA — Clock Phase
SPR1 and SPR0 — SPI Clock Rate Selects
8-6
RESET:
DWOM affects all six port D pins.
When the clock polarity bit is cleared and data is not being transferred, the SCK pin of
the master device has a steady state low value. When CPOL is set, SCK idles high.
Refer to Figure 8-2 and 8.2.1 Clock Phase and Polarity Controls.
The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relation-
ship between master and slave. The CPHA bit selects one of two different clocking
protocols. Refer to Figure 8-2 and 8.2.1 Clock Phase and Polarity Controls.
These two serial peripheral rate bits select one of four baud rates to be used as SCK
if the device is a master; however, they have no effect in the slave mode.
0 = SPI interrupt disabled
1 = SPI interrupt enabled
0 = SPI off
1 = SPI on
0 = Normal CMOS outputs
1 = Open-drain outputs
0 = Slave mode
1 = Master mode
SPIE
Bit 7
0
SPE
Freescale Semiconductor, Inc.
6
0
SPR[1:0]
For More Information On This Product,
0 0
0 1
1 0
1 1
SERIAL PERIPHERAL INTERFACE
DWOM
Go to: www.freescale.com
5
0
Divide By
E Clock
16
32
2
4
MSTR
4
0
E = 2 MHz (Baud)
CPOL
Frequency at
3
0
62.5 kHz
1.0 MHz
500 kHz
125 kHz
CPHA
2
1
SPR1
TECHNICAL DATA
U
1
$0028
SPR0
Bit 0
U

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