mc68hc11d0 Freescale Semiconductor, Inc, mc68hc11d0 Datasheet - Page 79

no-image

mc68hc11d0

Manufacturer Part Number
mc68hc11d0
Description
Mc68hc11d0 Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
mc68hc11d0CFB
Manufacturer:
FREESCALE
Quantity:
1 831
Part Number:
mc68hc11d0CFBE2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc68hc11d0CFBE3
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc68hc11d0CFBE3R
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc68hc11d0CFN
Manufacturer:
FREESCALE
Quantity:
1 831
Part Number:
mc68hc11d0CFN2
Manufacturer:
FREESCALE
Quantity:
8 831
Part Number:
mc68hc11d0CFN3
Manufacturer:
MOT
Quantity:
5 510
Part Number:
mc68hc11d0CFN3
Manufacturer:
LT
Quantity:
5 510
Part Number:
mc68hc11d0CFN3
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
mc68hc11d0CFNE2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc68hc11d0CFNE2R
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
8.1 Functional Description
TECHNICAL DATA
The serial peripheral interface (SPI), an independent serial communications sub-
system, allows the MCU to communicate synchronously with peripheral devices, such
as transistor-transistor logic (TTL) shift registers, liquid crystal diode (LCD) display
drivers, analog-to-digital converter subsystems, and other microprocessors. The SPI
is also capable of inter-processor communication in a multiple master system. The SPI
system can be configured as either a master or a slave device with data rates as high
as one half of the E-clock rate when configured as master, and as fast as the E-clock
rate when configured as slave.
The central element in the SPI system is the block containing the shift register and the
read data buffer. The system is single buffered in the transmit direction and double
buffered in the receive direction. This means that new data for transmission cannot be
written to the shifter until the previous transfer is complete; however, received data is
transferred into a parallel read data buffer so the shifter is free to accept a second se-
rial character. As long as the first character is read out of the read data buffer before
the next serial character is ready to be transferred, no overrun condition occurs. A sin-
gle MCU register address is used for reading data from the read data buffer, and for
writing data to the shifter.
The SPI status block represents the SPI status functions (transfer complete, write col-
lision, and mode fault) performed by the serial peripheral status register (SPSR). The
SPI control block represents those functions that control the SPI system through the
serial peripheral control register (SPCR).
Refer to Figure 8-1, which shows the SPI block diagram.
SERIAL PERIPHERAL INTERFACE
Freescale Semiconductor, Inc.
For More Information On This Product,
SERIAL PERIPHERAL INTERFACE
Go to: www.freescale.com
SECTION 8
8-1

Related parts for mc68hc11d0