mc68ec040v Freescale Semiconductor, Inc, mc68ec040v Datasheet - Page 193

• Manufacturer Part Number: mc68ec040v
• Description: M68040 User Manual
• Manufacturer: Freescale Semiconductor, Inc

Figure 7-33 illustrates a functional timing diagram for an arbitration of a relinquish and
retry operation. Figure 7-34 is a functional timing diagram for implicit ownership of the bus.
In Figure 7-33, the processor read access that begins in C1 is terminated at the end of C2
with a retry request and BG negated, forcing the processor to relinquish the bus and allow
the alternate master to access the bus. Note that the processor reasserts BR during C3
since the original access is pending again. After alternate bus master ownership, the bus
is granted to the processor to allow it to retry the access beginning in C7.
MOTOROLA
Figure 7-33. Arbitration During Relinquish and Retry Timing
ATTRIBUTES
*
AM indicates the alternate bus master.
TRANSFER
AM_BG
AM_BR
D31–D0
A31–A0
BCLK
R/W
TEA
TIP
BR
BG
BB
TS
TA
*
*
Freescale Semiconductor, Inc.
PROCESSOR
For More Information On This Product,
C1
C2
Go to: www.freescale.com
M68040 USER’S MANUAL
C3
C4
ALTERNATE
MASTER
C5
C6
C7
PROCESSOR
C8
7- 51