mc68ec040v Freescale Semiconductor, Inc, mc68ec040v Datasheet - Page 404

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mc68ec040v

Manufacturer Part Number
mc68ec040v
Description
M68040 User Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Once RSTI negates, the processor is internally held in reset for another 124 clocks
maximum. During the reset period, all signals that can be, are three-stated, and the rest
are driven to their inactive state. Once the internal reset signal negates, all bus signals
continue to remain in a high-impedance state until the processor is granted the bus.
Afterwards, the first bus cycle for reset exception processing begins. Figure C-2 illustrates
that the processor assumes implicit bus ownership before the first bus cycle begins.
For processor resets after the initial power-on reset, RSTI should be asserted for at least
10 clock periods. The Figure C-3 illustrates timings associated with a reset when the
processor is executing bus cycles. Note that BB and TIP (and TA if driven during a
snooped access) are negated before transitioning to a three-state level.
C- 8
CDIS, MDIS*,
NOTE: * Not on MC68EC040V.
IPL2–IPL0
SIGNALS
V CC
Figure C-2. MC68040V and MC68EC040V Initial Power-On Reset Timing
BCLK
RSTI
+5 V
BUS
0 V
TIP
BG
BR
TS
BB
MI
Undefined
Freescale Semiconductor, Inc.
For More Information On This Product,
CLOCKS
t 10
>
M68040 USER’S MANUAL
Go to: www.freescale.com
CLOCKS
2
CLOCKS
128
MOTOROLA

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