mpc8343e Freescale Semiconductor, Inc, mpc8343e Datasheet
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... Technical Data MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications The MPC8343E PowerQUICC™ II Pro is a next generation PowerQUICC II integrated host processor. The MPC8343E contains a PowerPC™ processor core built on Power Architecture™ technology with system logic for networking, storage, and general-purpose embedded applications. For functional characteristics of the processor, refer to the MPC8349E PowerQUICC™ ...
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... Full error checking and correction (ECC) support — Page mode support ( simultaneous open pages) — Contiguous or discontiguous memory mapping — Read-modify-write support — Sleep mode for self-refresh SDRAM — Auto refresh MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev e300 Core 2 C Interrupt ...
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... IEEE Std. 802.11i®, iSCSI, and IKE processing. The security engine contains four crypto-channels, a controller, and a set of crypto execution units (EUs): — Public key execution unit (PKEU) : – RSA and Diffie-Hellman algorithms MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Overview 3 ...
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... External PHY with UTMI, serial and UTMI+ low-pin interface (ULPI) • Local bus controller (LBC) — Multiplexed 32-bit address and data operating 133 MHz — Four chip selects support four external slaves MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Freescale Semiconductor ...
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... Programming model compatible with the original 16450 UART and the PC16550D • Serial peripheral interface (SPI) for master or slave • General-purpose parallel I/O (GPIO) — 39 parallel I/O pins multiplexed on various chip interfaces MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor 2 C interfaces 2 C-1 EPROM by boot sequencer embedded ...
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... Real-time clock — Software watchdog timer — Eight general-purpose timers • Designed to comply with IEEE Std. 1149.1™, JTAG boundary scan • Integrated PCI bus and SDRAM clock generation MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Freescale Semiconductor ...
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... Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8343E. The MPC8343E is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. ...
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... Electrical Characteristics 2.1.2 Power Supply Voltage Specification Table 2 provides the recommended operating conditions for the MPC8343E. Note that the values in Table 2 are the recommended and tested operating conditions. Proper device operation outside these conditions is not guaranteed. Table 2. Recommended Operating Conditions Characteristic Core supply voltage ...
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... Power Sequencing MPC8343E does not require the core supply voltage and I/O supply voltages to be applied in any particular order. Note that during the power ramp up, before the power supplies are stable, there may be a period of time that I/O pins are actively driven. After the power is stable, as long as PORESET is asserted, most I/O pins are three-stated ...
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... Power Characteristics 3 Power Characteristics The estimated typical power dissipation for the MPC8343E device is shown in l Core Frequency (MHz) PBGA 266 400 400 1 The values do not include I/O supply power (OV 2 Typical power is based on a voltage of V application. 3 Thermal solutions may need to design to a value higher than typical power based on the end application, T power ...
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... MHz, 32 bits 83 MHz, 32 bits 66 MHz, 32 bits 50 MHz, 32 bits TSEC I/O MII load = 25 pF GMII or TBI RGMII or RTBI USB 12 MHz 480 MHz Other I/O MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor DDR2 DDR1 (3.3 V) (3.3 V) (1.8 V) (2.5 V) — ...
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... PCI_SYNC_IN input current OV PCI_SYNC_IN input current 4.2 AC Electrical Characteristics The primary clock source for the MPC8343E can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. (CLKIN/PCI_CLK) AC timing specifications for the MPC8343E. Parameter/Condition CLKIN/PCI_CLK frequency CLKIN/PCI_CLK cycle time ...
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... This section describes the DC and AC electrical specifications for the reset initialization timing and electrical requirements of the MPC8343E. 5.1 RESET DC Electrical Characteristics Table 8 provides the DC electrical characteristics for the RESET pins of the MPC8343E. Table 8. RESET Pins DC Electrical Characteristics Characteristic Input high voltage Input low voltage ...
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... DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). A 2:1 ratio results in the minimum and an 8:1 ratio results in the maximum. 2. The csb_clk is determined by the CLKIN and system PLL ratio. See MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Min 0 — ...
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... Output leakage is measured with all outputs disabled Table 12 provides the DDR capacitance. Parameter/Condition Input/output capacitance: DQ, DQS Delta input/output capacitance: DQ, DQS Note: 1. This parameter is sampled MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor NOTE Section 23.1, “Part Numbers Fully Addressed by This Symbol Min GV 2.375 DD 0.49 × ...
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... MCK[n] cycle time, (MCK[n]/MCK[n] crossing) Skew between any MCK to ADDR/CMD ADDR/CMD output setup with respect to MCK ADDR/CMD output hold with respect to MCK MCS(n) output setup with respect to MCK MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev 2.5 V ± 5%. DD Symbol ...
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... Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC (MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the MPC8343E. 7. All outputs are referenced to the rising edge of MCK(n) at the pins of the MPC8343E. Note that t conventions described in note 1. MPC8343E PowerQUICC™ ...
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... DDR SDRAM measurement conditions. Table 15. DDR SDRAM Measurement Conditions Symbol OUT Notes: 1. Data input threshold measurement point. 2. Data output measurement point. MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev MCK[n] MCK[n] t MCK t AOSKEWmax) CMD t AOSKEW(min) ...
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... If a heavily loaded system is used, the DLL loop may need to be adjusted to meet setup requirements at the DRAM. Table 16. Expected Delays for Address/Command 4 devices (12 pF) 9 devices (27 pF) 36 devices (108 pF compensation capacitor 36 devices (108 pF compensation capacitor MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor t MCK t ,t DDKHAS ...
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... Low-level output voltage 7.2 DUART AC Electrical Specifications Table 18 provides the AC timing parameters for the DUART interface of the MPC8343E. Minimum baud rate Maximum baud rate Oversample rate Notes: 1. Actual attainable baud rate will be limited by the latency of interrupt processing. 2. The middle of a start bit is detected as the 8 ...
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... Input low current Notes: 1. The symbol this case, represents the MII pins not needed for RGMII or RTBI operation are powered by the OV MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Table 19. MII DC Electrical Characteristics Symbol Conditions 2 LV — ...
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... For example, the subscript of t represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise (fall). MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Symbol ...
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... MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise (fall). Figure 8 provides the AC test load for TSEC. Output MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor t MTX t ...
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... Duty cycle reference This symbol represents the external GTX_CLK125 and does not follow the original symbol naming convention. MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev MRX t ...
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... Transmitter) TXD[8:5][3:0] TXD[7:4][3:0] TX_CTL TX_CLK (At PHY) RXD[8:5][3:0] RXD[7:4][3:0] RX_CTL RX_CLK (At PHY) Figure 10. RGMII and RTBI AC Timing and Multiplexing Diagrams MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor t RGTH t SKRGT TXD[8:5] TXD[3:0] TXD[7:4] TXD[9] TXD[4] TXEN TXERR ...
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... Input high voltage Input low voltage Input high current Input low current Note: 1. The symbol this case, represents the LV IN MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Section 8.1, “Three-Speed Ethernet Controller (TSEC)— Table 24 and Symbol Conditions LV — ...
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... MHz, the delay is 58 ns). Figure 11 shows the MII management AC timing diagram. MDC MDIO (Input) MDIO (Output) Figure 11. MII Management Interface Timing Diagram MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor is 3.3 V ± 10% or 2.5 V ± 5 Symbol Min f — ...
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... USB 9 USB This section provides the AC and DC electrical specifications for the USB interface of the MPC8343E. 9.1 USB DC Electrical Characteristics Table 27 provides the DC electrical characteristics for the USB interface. Parameter High-level input voltage Low-level input voltage Input current = –100 μA High-level output voltage 100 μ ...
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... Figure 12 and Figure 13 provide the AC test load and signals for the USB, respectively. Output USB0_CLK/USB1_CLK/DR_CLK Input Signals Output Signals: MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor = 50 Ω Ω Figure 12. USB AC Test Load t USIVKH t t USKHOV USKHOX Figure 13 ...
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... Local Bus AC Electrical Specification Table 30 and Table 31 describe the general timing parameters of the local bus interface of the MPC8343E. Table 30. Local Bus General Timing Parameters—DLL On Parameter Local bus cycle time Input setup to local bus clock (except LUPWAIT) LUPWAIT input setup to local bus clock ...
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... Input hold from local bus clock LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor 1 Symbol ...
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... DLL bypass mode is not recommended for use at frequencies above 66 MHz. Figure 14 provides the AC test load for the local bus. Output MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Symbol t ...
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... LAD[0:31]/LDP[0:3] Input Signal: LGTA Output Signals: LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] LA[27:31]/LBCTL/LBCKE/LOE Output Signals: LAD[0:31]/LDP[0:3] LALE Figure 16. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode) MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor t LBIVKH t LBKHOV t LBKHOZ t t LBKHOV ...
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... UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) UPM Mode Output Signals: LCS[0:3]/LBS[0:3]/LGPL[0:5] Figure 18. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Bypass Mode) MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev LBKHOZ1 t LBKHOV1 t LBIVKH2 ...
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... LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) UPM Mode Output Signals: LCS[0:3]/LBS[0:3]/LGPL[0:5] Figure 19. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Bypass Mode) MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor t LBKHOZ t LBKHOV t LBIVKH ...
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... LCS[0:3]/LWE UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:3]/LBS[0:3]/LGPL[0:5] Figure 20. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (DLL Enabled) MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev LBKHOZ1 t LBKHOV1 t LBIVKH2 ...
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... JTAG external clock pulse width measured at 1.4 V JTAG external clock rise and fall times TRST assert time Input setup times: Boundary-scan data Input hold times: Boundary-scan data Valid times: Boundary-scan data MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Symbol Condition ...
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... Non-JTAG signal input timing with respect Non-JTAG signal output timing with respect Guaranteed by design and characterization. Figure 21 provides the AC test load for TDO and the boundary-scan outputs of the MPC8343E. Output Figure 21. AC Test Load for the JTAG Interface Figure 22 provides the JTAG clock input timing diagram ...
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... JTAG External Clock TDI, TMS t JTKLOX TDO TDO Output Data Valid Figure 25. Test Access Port Timing Diagram MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor VM t TRST VM = Midpoint Voltage (OV DD /2) Figure 23. TRST Timing Diagram VM t JTDVKH ...
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... Setup time for a repeated START condition Hold time (repeated) START condition (after this period, the first clock pulse is generated) Data setup time Data hold time: MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev interface of the MPC8343E. 2 Table 34 Electrical Characteristics of 3.3 V ± ...
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... For rise and fall times, the latter convention is used with the appropriate letter: R (rise (fall). 2. MPC8343E provides a hold time of at least 300 ns for the SDA signal (referred to the V the undefined region of the falling edge of SCL. ...
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... IN 13.2 PCI AC Electrical Specifications This section describes the general AC timing parameters of the PCI bus of the MPC8343E. Note that the PCI_CLK or PCI_SYNC_IN signal is used as the PCI input clock depending on whether the MPC8343E is configured as a host or agent device. Table 37. PCI AC Timing Specifications at 66 MHz ...
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... For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. Input timings are measured at the pin. Figure 28 provides the AC test load for PCI. Output MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor 2 Symbol Min t ...
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... PCI input AC timing diagram. CLK Input Figure 30 shows the PCI output AC timing diagram. CLK Output Delay High-Impedance Output MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev PCIVKH Figure 29. PCI Input AC Timing Diagram t PCKHOV Figure 30. PCI Output AC Timing Diagram t ...
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... Timers This section describes the DC and AC electrical specifications for the timers. 14.1 Timer DC Electrical Characteristics Table 39 provides the DC electrical characteristics for the MPC8343E timer pins, including TIN, TOUT, TGATE, and RTC_CLK. Table 39. Timer DC Electrical Characteristics Characteristic Input high voltage Input low voltage ...
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... Timings are measured at the pin. 2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by external synchronous logic. GPIO inputs must be valid for at least t MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Symbol ...
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... Timings are measured at the pin. 2. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by external synchronous logic. IPIC inputs must be valid for at least t MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Symbol ...
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... The symbols for timing specifications follow the pattern of t and t (first two letters of functional block)(reference)(state)(signal)(state) (NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X). MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Table 45. SPI DC Electrical Characteristics Symbol ...
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... SPIMISO (See Note) Output Signals: SPIMOSI (See Note) Note: The clock edge is selectable on SPI. Figure 33. SPI AC Timing in Master Mode (Internal Clock) Diagram MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor = 50 Ω Figure 31. SPI AC Test Load Table 46 ...
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... Package and Pin Listings 18 Package and Pin Listings This section details package parameters, pin assignments, and dimensions. The MPC8343E is available in a plastic ball grid array (PBGA). See Section 18.2, “Mechanical Dimensions for the MPC8343E PBGA.” 18.1 Package Parameters for the MPC8343E PBGA The package parameters are as provided in the following list. The package type × ...
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... A. 4.Datum A, the seating plane, is determined by the spherical crowns of the solder balls. Figure 34. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC8343E PBGA MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor ...
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... PCI1_REQ[1]/CPCI1_HS_ES PCI1_REQ[2:4] PCI1_GNT0 PCI1_GNT1/CPCI1_HS_LED PCI1_GNT2/CPCI1_HS_ENUM PCI1_GNT[3:4] M66EN MDQ[0:31] MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Table 47. MPC8343E (PBGA) Pinout Listing Package Pin Number PCI D20 B21 E19, D17, A16, A18, B17, B16, D16, B18, E17, E16, A15, C16, D15, D14, ...
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... SPARE1 SPARE2 LAD[0:31] LDP[0]/CKSTOP_OUT LDP[1]/CKSTOP_IN LDP[2] LDP[3] LA[27:31] MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Package Pin Number AG13, AE14, AH12, AH10, AE15 AH14 AE13, AH11 AG28, AG24, AF20, AG17 AG12 AE27, AE26, AE20, AH18 ...
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... GTM2_TGATE1 GPIO1[5]/GTM1_TOUT2/ GTM2_TOUT1 GPIO1[6]/GTM1_TIN3/GTM2_TIN4 GPIO1[7]/GTM1_TGATE3/ GTM2_TGATE4 GPIO1[8]/GTM1_TOUT3 GPIO1[9]/GTM1_TIN4/GTM2_TIN3 GPIO1[10]/GTM1_TGATE4/ GTM2_TGATE3 GPIO1[11]/GTM1_TOUT4/ GTM2_TOUT3 MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Package Pin Number J5, H4, F2, E1 F3, G4, D1 ...
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... IRQ[6]/GPIO2[18]/CKSTOP_OUT IRQ[7]/GPIO2[19]/CKSTOP_IN EC_MDC EC_MDIO EC_GTX_CLK125 Three-Speed Ethernet Controller (Gigabit Ethernet 1) TSEC1_COL/GPIO2[20] TSEC1_CRS/GPIO2[21] TSEC1_GTX_CLK TSEC1_RX_CLK MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Package Pin Number USB C28 F25 B28 C27 D26 E25 C26 ...
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... LSRCID[0:1] UART_SIN[1:2]/MSRCID[2:3]/ LSRCID[2:3] UART_CTS[1]/MSRCID4/LSRCID4 UART_CTS[2]/MDVAL/LDVAL UART_RTS[1:2] IIC1_SDA IIC1_SCL IIC2_SDA IIC2_SCL MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Package Pin Number U24 L28 W26, W24, Y28, Y27 N25 V28, V27, V26, W28 W27 N24 P28 ...
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... RTC/PIT_CLOCK CLKIN TCK TDI TDO TMS TRST TEST TEST_SEL QUIESCE PORESET HRESET SRESET THERM0 MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Package Pin Number SPI Clocks Y1, W3, W2, W1 JTAG H27 H28 ...
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... GND DD1 LV DD2 V DD MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Package Pin Number U1 AF9 U2 A2, B1, B2, D10, D18, E6, E14, E22, F9, F12, F15, F18, F21, F24, G5, H6, J23, L4, L6, L12, L13, L14, L15, L16, L17, M11, M12, M13, M14, M15, M16, M17, ...
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... This pin must be always be tied to GND. 7. This pin must always be pulled This pin must always be left no connected. 9. Thermal sensitive resistor. MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Package Pin Number B27, D3, D11, D19, E15, E23, F5, F8, ...
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... The primary clock source can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. When the MPC8343E is configured as a PCI host device, CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (÷2) and the multiplexors for PCI_SYNC_OUT and PCI_CLK_OUT ...
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... Unit TSEC1 2 TSEC2 Security core USB DR, USB MPH PCI and DMA complex MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Table 48 specifies which units have a configurable clock frequency. Table 48. Configurable Clock Units Default Frequency csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 ...
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... The local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn the csb_clk frequency (depending on RCWL[LBIUCM]). 19.1 System PLL Configuration The system PLL is controlled by the RCWL[SPMF] parameter. encodings for the system PLL. MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Table 49. Operating Frequencies for PBGA 266 MHz 200–266 2 Table 50 ...
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... PCI_CLK) and the internal coherent system bus clock (csb_clk). and Table 52 show the expected frequency values for the CSB frequency for select csb_clk to CLKIN/PCI_SYNC_IN ratios. MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor System PLL Multiplication RCWL[SPMF] Factor 1100 × ...
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... High High High High 1 CFG_CLKIN_DIV selects the ratio between CLKIN and PCI_SYNC_OUT. 2 CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode. MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev csb_clk : SPMF Input Clock 16.67 2 Ratio 0010 ...
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... RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300 core clock (core_clk). Table 53 not listed in Table 53 should be considered as reserved. MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor csb_clk : SPMF Input Clock 16.67 ...
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... MHz. 19.3 Suggested PLL Configurations Table 54 shows suggested PLL configurations for 33 and 66 MHz input clocks, when CFG_CLKIN_DIV is low at reset. MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev NOTE Table 53. e300 Core PLL Configuration core_clk : csb_clk Ratio PLL bypassed ...
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... The PLL configuration reference number is the hexadecimal representation of RCWL, bits 4–15 associated with the SPMF and COREPLL settings given in the table. 2 The input clock is CLKIN for PCI host mode or PCI_CLK for PCI agent mode. MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Table 54. Suggested PLL Configurations 333 MHz Device ...
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... Thermal 20 Thermal This section describes the thermal specifications of the MPC8343E. 20.1 Thermal Characteristics provides the package thermal characteristics for the 620 29 × PBGA of the MPC8343E. .Table 55 Table 55. Package Thermal Characteristics for PBGA Characteristic Junction-to-ambient natural convection on single-layer board (1s) Junction-to-ambient natural convection on four-layer board (2s2p) ...
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... The thermal characterization parameter is measured per the JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor – × ...
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... Wakefield, 53 × 53 × pin fin Wakefield, 53 × 53 × pin fin Wakefield, 53 × 53 × pin fin MEI, 75 × 85 × adjacent board, extrusion MEI, 75 × 85 × adjacent board, extrusion MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev θ θ ...
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... Internet: www.mei-thermal.com Tyco Electronics Chip Coolers™ P.O. Box 3668 Harrisburg, PA 17105-3668 Internet: www.chipcoolers.com Wakefield Engineering 33 Bridge St. Pelham, NH 03076 Internet: www.wakefield.com MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor 29 × PBGA Air Flow Thermal Resistance 2 m/s 6.6 1 m/s 6.9 603-224-9988 ...
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... From this case temperature, the junction temperature is determined from the junction-to-case thermal resistance MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev × θ ...
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... T = junction temperature (° case temperature of the package (° junction-to-case thermal resistance (°C/W) θ power dissipation (W) D MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Thermal 73 ...
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... Figure 36 shows the PLL power supply filter circuit MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev generates the platform clock from the externally supplied CLKIN ) Section 19.1, “System PLL Configuration.” ...
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... Decoupling Recommendations Due to large address and data buses and high operating frequencies, the MPC8343E can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the MPC8343E system, and the MPC8343E itself requires a clean, tightly regulated source of power ...
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... Note: Nominal supply voltages. See 21.6 Configuration Pin Multiplexing The MPC8343E power-on configuration options can be set through external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see the customer-visible configuration pins). These pins are used as output only pins in normal operation. However, while HRESET is asserted, these pins are treated as inputs, and the value on these pins is latched when PORESET deasserts ...
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... Pull-Up Resistor Requirements The MPC8343E requires high resistance pull-up resistors (10 kΩ is recommended) on open-drain pins, 2 including I C pins, the Ethernet Management MDIO pin, and IPIC interrupt pins. ...
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... Table 47: Deleted package pin number AD22 from NC signal row. 2 5/2005 Table 1: Typical values for power dissipation are changed to ‘TBD.’ MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Table 58. Document Revision History Substantive Change(s) changed the values in the Output Impedance column and added ...
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... Table 58. Document Revision History (continued) Revision Date 1 4/2005 Table 1: Addition of note 1. Table 47: Addition of Therm0 (B15). 0 4/2005 Initial release. MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Document Revision History Substantive Change(s) 79 ...
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... Each part number also contains a revision code that refers to the die mask revision number. For available frequency configuration parts including extended temperatures, refer to the MPC8343E product summary page on our website listed on the back cover of this document or, contact your local Freescale sales office. ...
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... Part Marking Parts are marked as in the example shown in Figure 38. Freescale Part Marking for PBGA Devices MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor . Figure 38 MPCnnnnetppaaar core/platform MHZ ATWLYYWW CCCCC *MMMMM YWWLAZ PBGA Notes : ATWLYYWW is the traceability code. ...
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... Ordering Information THIS PAGE INTENTIONALLY LEFT BLANK MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev Freescale Semiconductor ...
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... THIS PAGE INTENTIONALLY LEFT BLANK MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11 Freescale Semiconductor Ordering Information 83 ...
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... Denver, Colorado 80217 +1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Document Number: MPC8343EEC Rev. 11 07/2007 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...