mpc8343e Freescale Semiconductor, Inc, mpc8343e Datasheet - Page 78

• Manufacturer Part Number: mpc8343e
• Description: Mpc8343e Powerquicc
• Manufacturer: Freescale Semiconductor, Inc

Document Revision History
22 Document Revision History
Table 58
78
Revision
11
10
9
8
7
6
5
4
3
2
provides a revision history of this document.
MPC8343E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11
11/2005
10/2005
7/2007
3/2007
2/2007
8/2006
3/2006
9/2005
8/2005
5/2005
Date
In
USB to the seventh row.
In
paragraph, added a new paragraph.
Deleted Section 21.8, “JTAG Configuration Signals,” and Figure 43, “JTAG Interface Connection.”
In Section 23, “Ordering Information,” replaced first paragraph and added a note.
In Section 23.1, “Part Numbers Fully Addressed by this Document,” replaced first paragraph.
Page 1, updated first paragraph to reflect PowerQUICC II information. Updated note after second
paragraph.
In the features list in Section 1, “Overview,” corrected DDR data rate to show 266 MHz for PBGA parts
for all silicon revisions.
In Table 54, “Suggested PLL Configurations,” added the following row:
In Figure 38, “JTAG Interface Connection,” updated with new figure.
In Section 23, “Ordering Information,” replicated note from document introduction.
In Section 23.1, “Part Numbers Fully Addressed by this Document,” replaced third sentence of first
paragraph directing customer to product summary page for available frequency configuration parts.
Updated back page information.
Changed number of general purpose parallel I/O pins to 39 in Section 1, “Overview.”
Changed all references to revision 2.0 silicon to revision 3.0 silicon.
Changed VIH minimum value in Table 32, “JTAG Interface DC Electrical Characteristics,” to
OV
Section 2, “Electrical Characteristics,” moved to second section and all other section, table, and figure
numbering change accordingly.
Added Section 23.2, “Part Marking.”
Table 74: “Part Numbering Nomenclature:” Updated TBD values in note 1.
Added Table 75, “SVR Settings.”
Table 8, “CLKIN AC Timing Specifications:” Changed max rise and fall time from 1.2 to 2.3.
Table 34, “MII Management AC Timing Specifications:” Changed max value of t
170.
Table 38, “Local Bus General Timing Parameters—DLL on:” Changed min t
Table 40, “JTAG interface DC Electrical Characteristics:” Changed V
Updated values in Table 51, “Suggested PLL Configurations.”
Updated values in Table 46, “Operating Frequencies for PBGA.”
Changed classification of document to ‘Technical Data.’
Added Table 2, "MPC8343E Typical I/O Power Dissipation."
Table 1: Updated values for power dissipation that were TBD in Revision 2.
Table 47: Deleted package pin number AD22 from NC signal row.
Table 1: Typical values for power dissipation are changed to ‘TBD.’
Table
Section 21.7, “Pull-Up Resistor Requirements,”
Ref No: 823, SPMF: 1000, Core PLL: 0100011, 400-MHz Device Input Clock Freq: 33, CSB
Freq: 266, and Core Freq: 400.
DD
– 0.3.
3,
“Output Drive Capability,”
Table 58. Document Revision History
changed the values in the Output Impedance column and added
Substantive Change(s)
deleted last two paragraphs and after first
IH
input high voltage min to 2.0.
LBIVKH2
Freescale Semiconductor
MDKHDX
from 1.7 to 2.2.
from 70 to