mpc8378e Freescale Semiconductor, Inc, mpc8378e Datasheet - Page 67

• Manufacturer Part Number: mpc8378e
• Description: Powerquicc Ii Pro Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

15.2
Table 56
15.3
The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm)
of each other at all times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance.
15.4
Following is a summary of the specifications for the physical layer of PCI Express on this device. For
further details as well as the specifications of the transport and data link layer please use the PCI Express
Base Specification, Rev. 1.0a.
Freescale Semiconductor
REFCLK cycle time
REFCLK cycle-to-cycle jitter. Difference in the period of any
two adjacent REFCLK cycles.
REFCLK phase jitter peak-to-peak. Deviation in edge
location with respect to mean edge location.
SD_REF_CLK/_B cycle to cycle clock jitter (period jitter)
SD_REF_CLK/_B phase jitter peak-to-peak. Deviation in
edge location with respect to mean edge location.
Note:
1
2
3
All options provide serial interface bit rate of 1.5 and 3.0 Gbps.
In a frequency band from 150 kHz to 15 MHz, at BER of 10
Total peak-to-peak Deterministic Jitter “J
lists the PCI Express SerDes clock AC requirements.
AC Requirements for PCI Express SerDes Clocks
Clocking Dependencies
Physical Layer Specifications
The voltage levels of the transmitter and the receiver depend on the SerDes
control registers which should be programmed at the recommended values
for PCI Express protocol (that is, L1_nV
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 3
Parameter
Table 56. SD_REF_CLK and SD_REF_CLK AC Requirements
D
” should be less than or equal to 50 ps.
NOTE
-12
Symbol
t
t
.
REFCJ
t
REFPJ
t
t
CKPJ
CKCJ
REF
DD
= 1.0 V).
Min
–50
–50
—
—
—
Typical
10
—
—
—
—
Max
100
+50
100
+50
—
Unit
ns
ps
ps
ps
ps
PCI Express
Notes
2, 3
—
—
—
—
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