mpc8378e Freescale Semiconductor, Inc, mpc8378e Datasheet - Page 73

• Manufacturer Part Number: mpc8378e
• Description: Powerquicc Ii Pro Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

Unexpected Electrical Idle
Enter Detect Threshold
Integration Time
Total Skew
Note:
1
2
3
4
5
6
7
15.5
The Rx eye diagram in
Figure
measured with the compliance/test measurement load (see
eye diagram measured over a range of systems at the input receiver of any real PCI Express component.
The degraded eye diagram at the input receiver is due to traces internal to the package as well as silicon
Freescale Semiconductor
No test load is necessarily associated with this value.
Specified at the measurement point and measured over any 250 consecutive UIs. The test load in
as the Rx device when taking measurements (also refer to the receiver compliance eye diagram shown in
clocks to the Rx and Tx are not derived from the same reference clock, the Tx UI recovered from 3500 consecutive UI must be
used as a reference for the eye diagram.
A T
interconnect collected any 250 consecutive UIs. The TRx-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter
distribution in which the median and the maximum deviation from the median is less than half of the total. UI jitter budget
collected over any 250 consecutive Tx UIs. It should be noted that the median is not the same as the mean. The jitter median
describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged
time value. If the clocks to the Rx and Tx are not derived from the same reference clock, the Tx UI recovered from 3500
consecutive UI must be used as the reference for the eye diagram.
The receiver input impedance will result in a differential return loss greater than or equal to 10 dB with the D+ line biased to
300 mV and the D– line biased to –300 mV and a common mode return loss greater than or equal to 6 dB (no bias required)
over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference
impedance for return loss measurements for is 50 Ω to ground for both the D+ and D– line (that is, as measured by a vector
network analyzer with 50-Ω probes, see
measurement.
Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM) there
is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
The Rx DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps ensure
that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be measured
at 300 mV above the Rx ground.
It is recommended that the recovered Tx UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm
using a minimization merit function. Least squares and median deviation fits have worked well with experimental and simulated
data.
Rx-EYE
Parameter
48) in place of any real PCI Express Rx component. In general, the minimum receiver eye diagram
Receiver Compliance Eye Diagrams
= 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and
Table 58. Differential Receiver (Rx) Input Specifications (continued)
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 3
An unexpected electrical idle
(Vrx-diffp-p <
Vrx-idle-det-diffp-p) must be
recognized no longer than
Trx-idle-det-diff-entertime to
signal an unexpected idle
condition.
Skew across all lanes on a link.
This includes variation in the
length of SKP ordered set (e.g.
COM and one to five SKP
Symbols) at the Rx as well as
any delay differences arising
from the interconnect itself.
Figure 47
Comments
is specified using the passive compliance/test measurement load (see
Figure
48). Note that the series capacitors, C
T
RX-IDLE-DET-DIFF-
ENTERTIME
L
Symbol
RX-SKEW
Figure
48) is larger than the minimum receiver
Min
—
—
Tx
Typical
, is optional for the return loss
—
—
Figure 48
Max
10
20
Figure
Units
should be used
ms
ns
PCI Express
47). If the
Notes
—
—
73