mpc8378e Freescale Semiconductor, Inc, mpc8378e Datasheet - Page 83

• Manufacturer Part Number: mpc8378e
• Description: Powerquicc Ii Pro Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

20.2.2
The DC level requirement for the device SerDes reference clock inputs is different depending on the
signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described
below.
Freescale Semiconductor
•
•
— If the device driving the SDn_REF_CLK and SDn_REF_CLK inputs cannot drive 50 Ω to
The input amplitude requirement
— This requirement is described in detail in the following sections.
Differential Mode
— The input amplitude of the differential clock must be between 400 mV and 1600 mV
— For external DC-coupled connection, as described in
— For external AC-coupled connection, there is no common mode voltage requirement for the
SGND_SRDSn (xcorevss) DC, or it exceeds the maximum input current limitations, then it
must be AC-coupled off-chip.
differential peak-peak (or between 200 mV and 800 mV differential peak). In other words,
each signal wire of the differential pair must have a single-ended swing less than 800 mV and
greater than 200 mV. This requirement is the same for both external DC-coupled or
AC-coupled connection.
Clock Receiver
requirement for average voltage (common mode voltage) to be between 100 mV and 400 mV.
Figure 56
scheme.
clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver
and the SerDes reference clock receiver operate in different command mode voltages. The
SerDes reference clock receiver in this connection scheme has its common mode voltage set to
SGND_SRDSn. Each signal wire of the differential inputs is allowed to swing below and above
the command mode voltage (SGND_SRDSn).
input requirement for AC-coupled connection scheme.
DC Level Requirement for SerDes Reference Clocks
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 3
shows the SerDes reference clock input requirement for DC-coupled connection
Characteristics,” the maximum average current requirements sets the
SD n _REF_CLK
SD n _REF_CLK
Figure 55. Receiver of SerDes Reference Clocks
50 Ω
50 Ω
Figure 57
Input
Amp
Section 20.2.1, “SerDes Reference
shows the SerDes reference clock
High-Speed Serial Interfaces (HSSI)
83