mpc8379e Freescale Semiconductor, Inc, mpc8379e Datasheet - Page 115

• Manufacturer Part Number: mpc8379e
• Description: Powerquicc Ii Pro Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

26 Document Revision History
Table 84
Freescale Semiconductor
Revision
3
2
provides a revision history for this hardware specification.
03/2010 • Added
10/2009 • In
Date
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MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 3
Mode Only),” added table footnotes .
General Timing Parameters—PLL Bypass Mode,” corrected footnotes for t
Figure
“Input Signals: LAD[0:31]/LDP[0:3]” from the falling edge to the rising edge of LSYNC_IN.
heat spreader.
of open drain type pins.
AVDD_P pins.
Mode,” updated csb_clk frequencies available.
and DDR2 to 600 and 400 μA, respectively. Also, updated Note 1 and added Note 2.
“Min” and “Max”. Footnote 2 updated to state “T is the MCK clock period”.
DDR2 SDRAM Output AC Timing Specifications,” clarified that the frequency parameters are data rates.
Specifications,” corrected titles from “Transmitter” to “Receiver”.
to VDD pin.
range to 125–200.
respectively.
Table
Figure
Table
Table
Section 19.2, “SPI AC Timing Specifications,”
Table
Figure
Section 24.6, “Pull-Up Resistor Requirements,”
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
24, “Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (PLL Enable Mode),” shifted
Section 4.3, “eTSEC Gigabit Reference Clock Timing.”
34, “USB DC Electrical
69, “TePBGA II Pinout Listing,” added Note 15 to eTSEC pins.
74, “CSB Frequency Options for Host Mode,” and
39, “Local Bus General Timing Parameters—PLL Enable Mode,” and
69, “TePBGA II Pinout Listing,” updated the Pin Type column for AVDD_C, AVDD_L, and
81, “Part Numbering Nomenclature,” removed footnote to “e300 core Frequency.”
3, “Recommended Operating Conditions,” added “Operating temperature range” values.
5, “MPC8378E Power Dissipation
5, “MPC8378E Power Dissipation
5, “MPC8378E Power Dissipation
11, removed overbar from CFG_CLKIN_DIV.
17, “Current Draw Characteristics for MV
20, “DDR1 and DDR2 SDRAM Input AC Timing Specifications,” column headings renamed to
20, “DDR1 and DDR2 SDRAM Input AC Timing Specifications,” and
29, “RMII Transmit AC Timing Specifications,” updated t
57, Gen 1i/1.5G Transmitter AC Specifications,” and
69, “TePBGA II Pinout
71, “Operating Frequencies for TePBGA
76, “e300 Core PLL Configuration,” added 3.5:1 and 4:1 core_clk: csb_clk ratio options.
77, “Example Clock Frequency Combinations,” updated column heading to “DDR data rate” .
22, “Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (PLL Enable Mode),” and
60, “Mechanical Dimensions and Bottom Surface Nomenclature of the TEPBGA II,” added
Table 84. Document Revision History
Listing,”
Characteristics,”
Substantive Change(s)
removed pin THERM0; it is now Reserved. Also added 1.05 V
1
1
1
,” added a column for “Typical Application at T
,” corrected maximal application for 800/400 MHz to 4.3 W.
,” added a column for “Sleep Power at T
corrected t
and
II,”
REF
removed “Ethernet Management MDIO pin” from list
corrected “DDR2 memory bus frequency (MCK)”
Table
,” updated I
Table
NIKHOX
35, “USB General Timing Parameters (ULPI
Table
75, “CSB Frequency Options for Agent
MVREF
RMTDX
and t
59, Gen 2i/3G Transmitter AC
I to 2.0 ns.
NEKHOX
maximum value for both DDR1
LBOTOT1
Document Revision History
Table
Table
to t
NIKHOV
, t
21, “DDR1 and
j
40, “Local Bus
LBOTOT2
= 65°C (W)”.
j
and t
= 65°C (W)”.
, t
LBOTOT3
NEKHOV
115
,
.