mpc8379e Freescale Semiconductor, Inc, mpc8379e Datasheet - Page 98

• Manufacturer Part Number: mpc8379e
• Description: Powerquicc Ii Pro Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

Clocking
22 Clocking
Figure 61
The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on
whether the device is configured in PCI host or PCI agent mode. When the device is configured as a PCI
host device, CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (÷2) and the
multiplexors for PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input
selects whether CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCICOEn]
parameters select whether CFG_CLKIN_DIV is driven out on the PCI_CLK_OUTn signals.
PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to
synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN,
with equal delay to all PCI agent devices in the system, to allow the device to function. When the device
is configured as a PCI agent device, PCI_CLK is the primary input clock. When the device is configured
as a PCI agent device the CLKIN signal should be tied to GND.
98
CFG_CLKIN_DIV
shows the internal distribution of clocks within the MPC8379E.
CLKIN
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 3
System PLL
Figure 61. MPC8379E Clock Subsystem
e300 core
PCI Clock
csb_clk
Clock
Divider
Unit
csb_clk to rest
of the device
ddr_clk
lbiu_clk
Core PLL
to local bus
memory
controller
to DDR
memory
controller
Clock
LBIU
DDR
/n
DLL
Div
/2
core_clk
6
6
5
MCK[0:5]
MCK[0:5]
LCLK[0:2]
LSYNC_OUT
LSYNC_IN
PCI_CLK[0:4]
PCI_CLK/
PCI_SYNC_IN
PCI_SYNC_OUT
Freescale Semiconductor
DDR
Memory
Device
Local Bus
Memory
Device