mpc8306 Freescale Semiconductor, Inc, mpc8306 Datasheet
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mpc8306 Summary of contents
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... This document describes the electrical characteristics of MPC8306. To locate published errata or updates for this document, refer to the MPC8306 product summary page on our website listed on the back cover of this document or contact your local Freescale sales office. © 2011 Freescale Semiconductor, Inc. All rights reserved. ...
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... A new communications complex based on QUICC Engine technology forms the heart of the networking capability of the MPC8306. The QUICC Engine block contains several peripheral controllers and a 32-bit RISC controller. Protocol support is provided by the main workhorses of the device—the unified communication controllers (UCCs). A block diagram of the MPC8306 is shown in the following figure. 2x DUART I2C ...
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... In summary, the MPC8306 provides users with a highly integrated, fully programmable communications processor. This helps to ensure that a low-cost system solution can be quickly developed and offers flexibility to accommodate new standards and evolving system requirements. 1.1 Features The major features of the device are as follows: • ...
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... Provides two Write Enable signals to allow single byte write access to external 16-bit eLBC slave devices • Integrated programmable interrupt controller (IPIC) — Functional and programming compatibility with the MPC8260 interrupt controller — Support for external and internal discrete interrupt sources MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Freescale Semiconductor ...
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... C interfaces — Two-wire interface — Multiple-master support 2 — Master or slave I C mode support — On-chip digital filtering rejects spikes on the bus 2 — can be used as the boot sequencer MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor Overview 5 ...
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... Maintains a one-second count, unique over a period of thousands of years — Two possible clock sources: – External RTC clock (RTC_PIT_CLK) – CSB bus clock • IEEE Std. 1149.1™ compliant JTAG boundary scan MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Freescale Semiconductor ...
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... Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8306. The MPC8306 is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. ...
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... direction. 2. Minimum temperature is specified with T Temperature). 3. OVDD here refers to NVDDA, NVDDB, NVDDC, NVDDF, NVDDG, and NVDDH from the ball map. The following figure shows the undershoot and overshoot voltages at the interfaces of the MPC8306 G/ GND – 0 GND – ...
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... DDR2 signal DUART, system control, I2C, SPI, JTAG GPIO signals 2.1.4 Input Capacitance Specification The following table describes the input capacitance for the SYS_CLK_IN pin in the MPC8306. Parameter/Condition Input capacitance for all pins except SYS_CLK_IN and QE_CLK_IN Input capacitance for SYS_CLK_IN and QE_CLK_IN Note: 1 ...
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... Power Characteristics V 90% 0 PORESET Figure 3. 3 Power Characteristics The typical power dissipation for this family of MPC8306 devices is shown in the following table. Core QUICC Engine Frequency (MHz) Frequency (MHz) 133 133 200 233 266 233 333 233 Notes: 1. The values do not include I/O supply power (OV ...
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... The measurements were taken on the evaluation board using WC process silicon. 4 Clock Input Timing This section provides the clock input DC and AC electrical characteristics for the MPC8306. The rise/fall time on QUICC Engine input pins should not exceed 5 ns. This should be enforced especially on clock signals. Rise time refers to signal ...
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... Input hold time for POR config signals with respect to negation of HRESET Notes the clock period of the input clock applied to SYS_CLK_IN. For more details, see the MPC8306 PowerQUICC SYS_CLK_IN II Pro Integrated Communications Processor Family Reference Manual. 2. POR configuration signals consist of CFG_RESET_SOURCE[0:3]. ...
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... The following table provides the PLL lock times. Parameter/Condition PLL lock times 5.1 Reset Signals DC Electrical Characteristics The following table provides the DC electrical characteristics for the MPC8306 reset signals mentioned in Table 9. Table 11. Reset Signals DC Electrical Characteristics Characteristic Output high voltage Output low voltage ...
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... The following table provides the input AC timing specifications for the DDR2 SDRAM interface. Table 15. DDR2 SDRAM Input AC Timing Specifications At recommended operating conditions with GV Parameter Controller skew for MDQS—MDQ/MDM MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Symbol Min I – ...
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... At recommended operating conditions with GV Parameter MCK cycle time, (MCK/MCK crossing) ADDR/CMD output setup with respect to MCK ADDR/CMD output hold with respect to MCK MCS output setup with respect to MCK MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor of 1.8V ± 100mV. DD Symbol Min 266 MHz – ...
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... Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor follows the symbol conventions described in note 1. DDKHMP MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev 1.8V ± 100mV ...
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... MDQS MDQS The following figure shows the DDR2 SDRAM output timing diagram. MCK[n] MCK[n] ADDR/CMD MDQS[n] MDQ[x]/ MECC[x] Figure 6. DDR2 SDRAM Output Timing Diagram MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor MCK MCK t MCK t (max) = 0.6 ns DDKHMH t (min) = – ...
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... Local Bus 7 Local Bus This section describes the DC and AC electrical specifications for the local bus interface of the MPC8306. 7.1 Local Bus DC Electrical Characteristics The following table provides the DC electrical characteristics for the local bus interface. Table 17. Local Bus DC Electrical Characteristics Parameter High-level input voltage Low-level input voltage = – ...
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... LCLK[n] Input Signals: LAD[0:15] Input Signal: LGTA Output Signals: LBCTL/LBCKE/LOE Output Signals: LAD[0:15] LALE MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor = 50 Figure 7. Local Bus AC Test Load t LBIVKH t LBKHOV t ...
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... GPCM Mode Output Signals: LCS[0:3]/LWE UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:15]/LDP[0:3] UPM Mode Output Signals: LCS[0:3]/LBS[0:1]/LGPL[0:5] Figure 9. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev LBKHOZ t LBKHOV t LBIVKH t ...
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... MDC are specified in Section 8.3, “Ethernet Management Interface Electrical Characteristics.” 8.1.1 DC Electrical Characteristics All MII and RMII drivers and receivers comply with the DC parametric attributes specified in The following table. MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor t LBKHOZ t LBKHOV ...
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... For example, the subscript of t MTX used with the appropriate letter: R (rise (fall). MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Symbol Conditions OV — ...
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... For example, the subscript of t represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used MRX with the appropriate letter: R (rise (fall). MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor = 50 Figure 11 ...
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... For example, the subscript of t convention is used with the appropriate letter: R (rise (fall). The following figure provides the AC test load. Output MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev MRX t ...
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... Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of t the latter convention is used with the appropriate letter: R (rise (fall). MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor t ...
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... The following table provides the MII management AC timing specifications. Table 25. MII Management AC Timing Specifications At recommended operating conditions with OV Parameter/Condition MDC frequency MDC period MDC clock pulse width high MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev RMX t t RMXF ...
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... R (rise (fall). The following figure shows the MII management AC timing diagram. MDC MDIO (Input) MDIO (Output) Figure 17. MII Management Interface Timing Diagram MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor is 3.3 V ± 300mV Symbol Min t ...
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... PowerQUICC II Pro Integrated Communications Processor Family Reference Manual, for a description of TMR_CTRL registers needs least two times of clock period of clock selected by TMR_CTRL[CKSEL]. See the MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Reference Manual, for a description of TMR_CTRL registers. 3. The maximum value of t ...
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... The following table provides the DC electrical characteristics for the MPC8306 TDM/SI. Table 28. TDM/SI DC Electrical Characteristics Characteristic Output high voltage Output low voltage Input high voltage Input low voltage Input current MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor t T1588CLKOUT t T1588CLKOUTH t T1588OV T1588CLKOUT Figure 18 ...
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... HDLC This section describes the DC and AC electrical specifications for the high level data link control (HDLC), of the MPC8306. MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Table 29. TDM/SI AC Timing Specifications (first two letters of functional block)(signal)(state)(reference)(state) for outputs ...
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... HDLC DC Electrical Characteristics The following table provides the DC electrical characteristics for the MPC8306 HDLC protocol. Characteristic Output high voltage Output low voltage Input high voltage Input low voltage Input current 10.2 HDLC AC Timing Specifications The following table provides the input and output AC timing specifications for HDLC protocol. ...
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... The following table provides the DC electrical characteristics for the USB interface. 11.1.2 USB AC Electrical Specifications The following table describes the general timing parameters of the USB interface. MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Table 31. Note that although the specifications ...
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... The following figures provide the AC test load and signals for the USB, respectively. Output USBDR_CLK Input Signals t Output Signals MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor Table 32. USB DC Electrical Characteristics Symbol ...
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... DUART 12 DUART This section describes the DC and AC electrical specifications for the DUART interface of the MPC8306. 12.1 DUART DC Electrical Characteristics The following table provides the DC electrical characteristics for the DUART interface of the MPC8306. Table 34. DUART DC Electrical Characteristics Parameter High-level input voltage Low-level input voltage – ...
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... MMC Full-speed/High-speed mode SD_CLK clock low time—Full-speed/High-speed mode SD_CLK clock high time—Full-speed/High-speed mode SD_CLK clock rise and fall times Input setup times: SD_CMD, SD_DATx, SD_CD to SD_CLK MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor = 3 Symbol Condition V — ...
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... The following figure provides the data and command input/output timing diagram. VM SD_CK External Clock SD_DAT/CMD Inputs SD_DAT/CMD Outputs Figure 28. eSDHC Data and Command Input/Output Timing Diagram Referenced to Clock MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev 3 Symbol t SHSIXKH t ...
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... It is referenced in IN 14.2 FlexCAN AC Timing Specifications The following table provides the AC timing specifications for the FlexCAN interface. For recommended operating conditions, see Parameter Min Baud rate MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor Table 2 Symbol ...
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... Output voltage (open drain or open collector) condition = 3 mA sink current capacitance of one bus line in pF Refer to the MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Reference Manual for information on the digital filter used. 4. I/O pins obstructs the SDA and SCL lines ...
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... For rise and fall times, the latter convention is used with the appropriate letter: R (rise (fall). 2. MPC8306 provides a hold time of at least 300 ns for the SDA signal (referred to the V undefined region of the falling edge of SCL. ...
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... Timers 16 Timers This section describes the DC and AC electrical specifications for the timers of the MPC8306. 16.1 Timer DC Electrical Characteristics The following table provides the DC electrical characteristics for the MPC8306 timer pins, including TIN, TOUT, TGATE, and RTC_PIT_CLK. Characteristic Output high voltage Output low voltage ...
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... GPIO This section describes the DC and AC electrical specifications for the GPIO of the MPC8306. 17.1 GPIO DC Electrical Characteristics The following table provides the DC electrical characteristics for the MPC8306 GPIO. Characteristic Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage ...
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... IPIC inputs are required to be valid for at least t in edge triggered mode. 19 SPI This section describes the DC and AC electrical specifications for the SPI of the MPC8306. 19.1 SPI DC Electrical Characteristics The following table provides the DC electrical characteristics for the MPC8306 SPI. ...
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... Figure 35 represent the AC timing from generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor Table 48. SPI DC Electrical Characteristics Symbol ...
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... The following table provides the DC electrical characteristics for the IEEE Std. 1149.1 (JTAG) interface of the MPC8306. Table 50. JTAG Interface DC Electrical Characteristics Characteristic Output high voltage Output low voltage Output low voltage MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev NEIXKH t NEKHOV t ...
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... Input low voltage Input current 20.2 JTAG AC Electrical Characteristics This section describes the AC electrical specifications for the IEEE Std. 1149.1 (JTAG) interface of the MPC8306. The following table provides the JTAG AC timing specifications as defined in through Figure 40. Table 51. JTAG AC Timing Specifications (Independent of SYS_CLK_IN) At recommended operating conditions (see ...
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... Non-JTAG signal input timing with respect Non-JTAG signal output timing with respect Guaranteed by design and characterization. The following figure provides the AC test load for TDO and the boundary-scan outputs of the MPC8306. Output Figure 36. AC Test Load for the JTAG Interface The following figure provides the JTAG clock input timing diagram ...
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... Data Outputs The following figure provides the test access port timing diagram. JTAG External Clock TDI, TMS t JTKLOX TDO TDO Output Data Valid MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor VM t JTDVKH t JTKLDV t JTKLDZ VM = Midpoint Voltage (OV DD /2) Figure 39 ...
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... Package and Pin Listings 21 Package and Pin Listings This section details package parameters, pin assignments, and dimensions. The MPC8306 is available in a thermally enhanced MAPBGA (mold array process-ball grid array); see Parameters for the MPC8306,” for information on the MAPBGA. 21.1 Package Parameters for the MPC8306 The package parameters are as provided in the following list ...
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... Dimensions and tolerances per ASME Y14.5M-1994. 3. Maximum solder ball diameter measured parallel to datum A. 4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls. MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor Package and Pin Listings ...
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... MEMC_MDM[1] MEMC_MDQS[0] MEMC_MDQS[1] MEMC_MBA[0] MEMC_MBA[1] MEMC_MBA[2] MEMC_MA[0] MEMC_MA[1] MEMC_MA[2] MEMC_MA[3] MEMC_MA[4] MEMC_MA[5] MEMC_MA[6] MEMC_MA[7] MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev MPC8306 Pinout Listing Table 52. Package Pin Number DDR Memory Controller Interface AB1 AA1 ...
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... LAD[1] LAD[2] LAD[3] LAD[4] LAD[5] LAD[6] LAD[7] LAD[8] LAD[9] LAD[10] LAD[11] LAD[12] LAD[13] LAD[14] LAD[15] LA[16] MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor MPC8306 Pinout Listing (continued) Package Pin Number Pin Type ...
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... LGPL[5] LWE_B[0] LWE_B[1] LBCTL LALE TCK TDI TDO TMS TRST_B TEST_MODE HRESET_B PORESET_B MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev MPC8306 Pinout Listing (continued) Package Pin Number Pin Type B14 A14 A15 A16 B16 A17 B17 A18 ...
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... QE_TRB_I USBDR_TXDRXD[2]/UART1_SOUT[2]/ UART1_RTS_B1/QE_BRG[1] USBDR_TXDRXD[3]/UART1_SIN[2]/ UART1_CTS_B1/QE_BRG[2] USBDR_TXDRXD[4]/GPIO[34]/QE_BRG[3] USBDR_TXDRXD[5]/GPIO[35]/QE_BRG[4] USBDR_TXDRXD[6]/GPIO[36]/QE_BRG[9] MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor MPC8306 Pinout Listing (continued) Package Pin Number Pin Type Clock Interface P23 R23 ...
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... FEC1_COL/GTM1_TIN[1]/GPIO[16] FEC1_CRS/GTM1_TGATE1_B/GPIO[17] FEC1_RX_CLK/GPIO[18] FEC1_RX_DV/GTM1_TIN[2]/GPIO[19] FEC1_RX_ER/GTM1_TGATE[2]_B/GPIO[20] FEC1_RXD0/GPIO[21] FEC1_RXD1/GTM1_TIN[3]/GPIO[22] FEC1_RXD2/GTM1_TGATE[3]_B/GPIO[23] FEC1_RXD3/GPIO[24] FEC1_TX_CLK/GTM1_TIN4/GPIO[25] FEC1_TX_EN/GTM1_TGATE[4]_B/GPIO[26] MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev MPC8306 Pinout Listing (continued) Package Pin Number Pin Type Y5 DUART C23 F19 D23 ...
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... FEC2_TXD3/GPIO[47] FEC3_COL/GPIO[48] FEC3_CRS/GPIO[49] FEC3_RX_CLK/GPIO[50] FEC3_RX_DV/FEC1_TMR_TX_ESFD/GPIO[51] FEC3_RX_ER/FEC1_TMR_RX_ESFD/GPIO[52] FEC3_RXD0/FEC2_TMR_TX_ESFD/GPIO[53] FEC3_RXD1/FEC2_TMR_RX_ESFD/GPIO[54] FEC3_RXD2/TSEC_TMR_TRIG1/GPIO[55] FEC3_RXD3/TSEC_TMR_TRIG2/GPIO[56] FEC3_TX_CLK/TSEC_TMR_CLK/GPIO[57] FEC3_TX_EN/TSEC_TMR_GCLK/GPIO[58] FEC3_TX_ER/TSEC_TMR_PP1/GPIO[59] MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor MPC8306 Pinout Listing (continued) Package Pin Number Pin Type AC17 AB16 AC16 AC15 AB14 FEC2/GPIO AC14 ...
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... HDLC2_CD_B/GPIO[20]/TDM2_TFS HDLC2_CTS_B/GPIO[21]/TDM2_RFS HDLC2_RTS_B/GPIO[22]/TDM2_STROBE_B/ CFG_RESET_SOURCE[3] AV DD1 AV DD2 AV DD3 MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev MPC8306 Pinout Listing (continued) Package Pin Number Pin Type R20 T22 T23 T20 HDLC/GPIO/TDM U23 U22 AC22 W18 ...
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... This pin is an open drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin This pin is an open drain signal. A weak pull-up resistor (2-10 kΩ) should be placed on this pin This pin has weak pull-up that is always enabled. MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor MPC8306 Pinout Listing ...
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... Clocking 22 Clocking The following figure shows the internal distribution of clocks within the MPC8306. SYS_CLK_IN QE_CLK_IN QE PLL The primary clock source for MPC8306 is SYS_CLK_IN. Figure 43. MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Figure 42. MPC8306 Clock Subsystem e300c3 core ...
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... LBC clock divider to create the external local bus clock outputs (LCLK). The LBC clock divider ratio is controlled by LCRR[CLKDIV]. For more information, see the LBC Bus Clock and Clock Ratios section in the MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Reference Manual. ...
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... These units have a default clock ratio that can be configured by a memory mapped register after the device comes out of reset. The following table specifies which units have a configurable clock frequency. For detailed description, refer to the “System Clock Control Register (SCCR)” section in the MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Reference Manual. Unit ...
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... RCWL[COREPLL] 0-1 2-5 nn 0000 00 0001 01 0001 10 0001 11 0001 MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor Table 55. System PLL Multiplication Factors System PLL Multiplication Factor Table 56. CSB Frequency Options 25 2:1 3:1 4:1 5:1 125 6:1 Table 57. e300 Core PLL Configuration core_clk : csb_clk Ratio ...
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... QUICC Engine PLL. Table 58. QUICC Engine PLL Multiplication Factors RCWL[CEPMF] RCWL[CEPDF] 00000–00001 0 00010 0 00011 0 00100 0 00101 0 00110 0 MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev core_clk : csb_clk Ratio 6 1 1.5:1 1 1.5:1 1 1.5:1 1 1.5:1 0 2:1 0 2:1 ...
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... Suggested PLL Configurations To simplify the PLL configurations, the MPC8306 might be separated into two clock domains. The first domain contains the CSB PLL and the core PLL. The core PLL is connected serially to the CSB PLL, and has the csb_clk as its input clock. The second clock domain has the QUICC Engine PLL. The clock domains are independent, and each of their PLLs is configured separately ...
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... Clocking Core Conf No. SPMF PLL 1 0100 0000100 2 0010 0000100 3 0100 0000101 4 0101 0000101 5 0010 0000101 MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Table 60. Suggested PLL Configurations Input Clock CEPMF CEDF Frequency (MHz) 0111 0 33.33 0111 1 66.67 0111 0 33.33 1001 0 25 ...
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... Estimation of Junction Temperature with Junction-to-Ambient Thermal Resistance An estimation of the chip junction temperature, T where junction temperature (C) J MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor Board type Single-layer board (1s) Four-layer board (2s2p) Single-layer board (1s) Four-layer board (2s2p) — ...
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... To determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter ( measurement of the temperature at the top center of the package case using the following equation: where junction temperature (C) J MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev ...
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... Avoid attachment forces which would lift the edge of the package or peel the package from the board. Such peeling forces reduce the solder joint MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor ...
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... PLL ratio configuration bits as described in • The QUICC Engine PLL (AV Engine block generates or uses external sources for all required serial interface clocks. MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev ...
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... Decoupling Recommendations Due to large address and data buses, and high operating frequencies, the MPC8306 can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the MPC8306 system, and MPC8306 itself requires a clean, tightly regulated source of power ...
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... V = (1/(1/R 2 – 1). The drive current is then I source term 1 2 MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev trimmed until the voltage at the pad equals )/ Pad Data R Figure 45. Driver Impedance Measurement I ...
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... Configuration Pin Multiplexing The MPC8306 provides the user with power-on configuration options which can be set through the use of external pull-up or pull-down resistors of 4.7 k on certain output pins (Refer to the “Reset, Clocking and Initialization” of MPC8306S PowerQUICC II Pro Integrated Communications Processor Family Reference Manual) ...
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... Parts are marked as in the example shown in the following figure. Figure 46. Freescale Part Marking for MAPBGA Devices The following table shows the SVR Settings. Device MPC8306 Note: PVR = 0x8085_0020 MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev Table 63. Part Numbering Nomenclature VM AF e300 Core ...
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... In Part Nomenclature field for QUICC Engine frequency, C now denotes 233 MHz. Updated • Added SPISEL_BOOT in MPC8306 Pin out Listing • Corrected SPISEL Pin Type in 0 03/2011 Initial Release MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2 Freescale Semiconductor Table 65. Document Revision History Substantive Change(s) Table 63. ...
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... Literature Distribution Center 1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Document Number: MPC8306EC Rev. 2 09/2011 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...