mpc8306 Freescale Semiconductor, Inc, mpc8306 Datasheet - Page 60

• Manufacturer Part Number: mpc8306
• Description: Powerquicc Ii Pro Integrated Communications Processor Family Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

Clocking
In addition, some of the internal units may be required to be shut off or operate at lower frequency than
the csb_clk frequency. These units have a default clock ratio that can be configured by a memory mapped
register after the device comes out of reset.
The following table specifies which units have a configurable clock frequency. For detailed description,
refer to the “System Clock Control Register (SCCR)” section in the MPC8306 PowerQUICC II Pro
Integrated Communications Processor Family Reference Manual.
The following table provides the maximum operating frequencies for the MPC8306 MAPBGA under
recommended operating conditions (see
22.2
The system PLL is controlled by the RCWL[SPMF] parameter.
encodings for the system PLL.
As described in
configuration word low select the ratio between the primary clock input (SYS_CLK_IN) and the internal
60
I2C,SDHC, USB, DMA Complex
e300 core frequency (core_clk)
Coherent system bus frequency (csb_clk)
QUICC Engine frequency (qe_clk)
DDR2 memory bus frequency (MCLK)
Local bus frequency (LCLKn)
Notes:
1. The SYS_CLK_IN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting
2. The DDR2 data rate is 2× the DDR2 memory bus frequency.
3. The local bus frequency is 1/2, 1/4, or 1/8 of the lb_clk frequency (depending on LCRR[CLKDIV]) which is in turn 1× or 2×
csb_clk, MCLK, LCLK, and core_clk frequencies do not exceed their respective maximum or minimum operating
frequencies.
the csb_clk frequency (depending on RCWL[LBCM]).
MPC8306 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2
System PLL Configuration
Setting the clock ratio of these units must be performed prior to any access
to them.
System PLL VCO frequency = 2 × (CSB frequency) × (System PLL VCO
divider). The VCO divider needs to be set properly so that the System PLL
VCO frequency is in the range of 450–750 MHz.
Section 22, “Clocking,”
Unit
Characteristic
3
Table 54. Operating Frequencies for MAPBGA
2
1
Table 53. Configurable Clock Units
Table
the LBCM, DDRCM, and SPMF parameters in the reset
Default Frequency
2).
csb_clk
NOTE
NOTE
Max Operating Frequency
Off, csb_clk, csb_clk/2, csb_clk/3
Table 55
266
133
233
167
66
shows the multiplication factor
Options
Freescale Semiconductor
MHz
MHz
MHz
MHz
MHz
Unit