mpc755ed Freescale Semiconductor, Inc, mpc755ed Datasheet
mpc755ed
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mpc755ed Summary of contents
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... The MPC745 is identical to the MPC755 except it does not support the L2 cache interface. Figure 1 shows a block diagram of the MPC755. © Freescale Semiconductor, Inc., 2006. All rights reserved. 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4. Electrical and Thermal Characteristics . . . . . . . . . . . . 6 5 ...
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Overview MPC755 RISC Microprocessor Hardware Specifications, Rev Figure 1. MPC755 Block Diagram Freescale Semiconductor ...
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Features This section summarizes features of the MPC755 implementation of the PowerPC architecture. Major features of the MPC755 are as follows: • Branch processing unit — Four instructions fetched per clock — One branch processed per cycle (plus resolving ...
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Features — Three-cycle latency, one-cycle throughput, double-precision add — Four-cycle latency, two-cycle throughput, double-precision multiply-add • System unit — Executes CR logical instructions and miscellaneous system instructions — Special register transfer instructions • Load/store unit — One-cycle load or store ...
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Selectable interface voltages of 2.5 and 3.3 V — Parity checking on both L2 address and data • Memory management unit — 128-entry, two-way set-associative instruction TLB — 128-entry, two-way set-associative data TLB — Hardware reload for TLBs — ...
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Electrical and Thermal Characteristics Packages Core power supply I/O power supply 4 Electrical and Thermal Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC755. 4.1 DC Electrical Characteristics Table 1 through Table 7 ...
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Figure 2 shows the allowable undershoot and overshoot voltage on the MPC755. (L2)OV + 20% DD (L2) (L2) GND GND – 0.3 V GND – 0.7 V The MPC755 provides several I/O voltages to support ...
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Electrical and Thermal Characteristics Table 3 provides the recommended operating conditions for the MPC755. Table 3. Recommended Operating Conditions Characteristic Core supply voltage PLL supply voltage L2 DLL supply voltage Processor bus supply BVSEL = 1 voltage L2 bus supply ...
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Characteristic Junction-to-ambient thermal resistance, natural convection Junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board Junction-to-ambient thermal resistance, 200 ft/min airflow, single-layer (1s) board Junction-to-ambient thermal resistance, 200 ft/min airflow, four-layer (2s2p) board Junction-to-board thermal resistance Junction-to-case thermal resistance Notes: 1. ...
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Electrical and Thermal Characteristics At recommended operating conditions (see Characteristic Temperature range Comparator settling time Resolution Accuracy Notes: 1. The temperature is the junction temperature of the die. The thermal assist unit’s raw output does not indicate an absolute temperature, ...
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Table 6. DC Electrical Specifications (continued) At recommended operating conditions (see Characteristic Capacitance MHz in Notes: 1. Nominal voltages; see Table 3 for recommended operating conditions. 2. For processor bus signals, the reference ...
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Electrical and Thermal Characteristics 4.2 AC Electrical Characteristics This section provides the AC electrical characteristics for the MPC755. After fabrication, functional parts are sorted by maximum processor core frequency as shown in and tested for conformance to the AC specifications ...
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Figure 3 provides the SYSCLK input timing diagram. SYSCLK VM 4.2.2 Processor Bus AC Specifications Table 9 provides the processor bus AC timing specifications for the MPC755 as defined in Figure 6. Timing specifications for the L2 bus are provided ...
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Electrical and Thermal Characteristics Figure 4 provides the mode select input timing diagram for the MPC755. HRESET Mode Signals Figure 5 provides the AC test load for the MPC755. Output MPC755 RISC Microprocessor Hardware Specifications, Rev ...
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Table 10. Processor Bus AC Timing Specifications At recommended operating conditions (see Parameter Setup times: All inputs Input hold times: TLBISYNC, MCP, SMI Input hold times: All inputs, except TLBISYNC, MCP, SMI Valid times: All outputs Output hold times: All ...
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Electrical and Thermal Characteristics Figure 6 provides the input/output timing diagram for the MPC755. SYSCLK All Inputs All Outputs (Except TS, ABB, ARTRY, DBB) TS, ABB, DBB ARTRY 4.2.3 L2 Clock AC Specifications The L2CLK frequency is programmed by the ...
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SRAM. Note that revisions of the MPC755 prior to Rev. 2.8 (Rev. E) were limited in performance, and were typically limited to 175 MHz with similarly-rated SRAM. For more information, see “Part Numbers Not Fully Addressed by This Document.” Freescale ...
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Electrical and Thermal Characteristics Table 11. L2CLK Output AC Timing Specification At recommended operating conditions (see Parameter L2CLK frequency L2CLK cycle time L2CLK duty cycle Internal DLL-relock time DLL capture window L2CLK_OUT output-to-output skew L2CLK_OUT output jitter Notes: 1. L2CLK ...
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The L2CLK_OUT timing diagram is shown in L2 Single-Ended Clock Mode L2CLK_OUTA L2CLK_OUTB L2SYNC_OUT L2 Differential Clock Mode L2CLK_OUTB L2CLK_OUTA L2SYNC_OUT Figure 7. L2CLK_OUT Output Timing Diagram 4.2.4 L2 Bus AC Specifications Table 12 provides the L2 bus interface AC ...
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Electrical and Thermal Characteristics Table 12. L2 Bus Interface AC Timing Specifications (continued) At recommended operating conditions (see Parameter L2SYNC_IN to high impedance: All outputs when L2CR[14–15 All outputs when L2CR[14–15 All outputs when L2CR[14–15] = ...
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Figure 9 shows the L2 bus output timing diagrams for the MPC755. L2SYNC_IN All Outputs L2DATA BUS Figure 10 provides the AC test load for L2 interface of the MPC755. Output MPC755 RISC Microprocessor Hardware Specifications, Rev. 8 Freescale Semiconductor ...
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Electrical and Thermal Characteristics 4.2.5 IEEE 1149.1 AC Timing Specifications Table 13 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 15. Table 13. JTAG AC Timing Specifications (Independent of SYSCLK) At recommended operating conditions (see Parameter ...
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Figure 12 provides the JTAG clock input timing diagram. TCLK VM Figure 12. JTAG Clock Input Timing Diagram Figure 13 provides the TRST timing diagram. VM TRST Figure 14 provides the boundary-scan timing diagram. VM TCK Boundary Data Inputs Boundary ...
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Electrical and Thermal Characteristics Figure 15 provides the test access port timing diagram. TCK VM TDI, TMS TDO TDO Figure 15. Test Access Port Timing Diagram MPC755 RISC Microprocessor Hardware Specifications, Rev IVJH t JLOV t JLOH ...
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Pin Assignments Figure 16 (in Part A) shows the pinout of the MPC745, 255 PBGA package as viewed from the top surface. Part B shows the side profile of the PBGA package to indicate the direction of the top ...
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Pin Assignments Figure 17 (in Part A) shows the pinout of the MPC755, 360 PBGA and 360 CBGA packages as viewed from the top surface. Part B shows the side profile of the PBGA and CBGA package to indicate the ...
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Pinout Listings Table 14 provides the pinout listing for the MPC745, 255 PBGA package. Table 14. Pinout Listing for the MPC745, 255 PBGA Package Signal Name A[0:31] C16, E4, D13, F2, D14, G1, D15, E2, D16, D4, E13, G2, ...
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Pinout Listings Table 14. Pinout Listing for the MPC745, 255 PBGA Package (continued) Signal Name INT B15 L1_TSTCLK D11 L2_TSTCLK D12 LSSD_MODE B10 MCP C13 NC (No Connect) B7, B8, C3, C6, C8, D5, D6, H4, J16, A4, A5, A2, ...
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Table 14. Pinout Listing for the MPC745, 255 PBGA Package (continued) Signal Name VOLTDET F3 Notes supplies power to the processor bus, JTAG, and all control signals; and V DD the PLL (after filtering to become AV signal ...
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Pinout Listings Table 15. Pinout Listing for the MPC755, 360 BGA Package (continued) Signal Name DH[0:31] W12, W11, V11, T9, W10, U9, U10, M11, M9, P8, W7, P9, W9, R10, W6, V7, V6, U8, V9, T7, U7, R7, U6, W5, ...
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Table 15. Pinout Listing for the MPC755, 360 BGA Package (continued) Signal Name L2ZZ G17 LSSD_MODE F9 MCP B11 NC (No Connect) B3, B4, B5, W19, K9, K11 OV D5, D8, D12, E4, E6, E9, E11, F5, H4, J5, L5, ...
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Package Description Table 15. Pinout Listing for the MPC755, 360 BGA Package (continued) Signal Name VOLTDET K13 Notes supplies power to the processor bus, JTAG, and all control signals except the L2 cache controls (L2CE, L2WE, and DD ...
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Package Parameters for the MPC745 PBGA The package parameters are as provided in the following list. The package type is 21 × 21 mm, 255-lead plastic ball grid array (PBGA). Package outline Interconnects Pitch Minimum module height Maximum module ...
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Package Description 7.3 Package Parameters for the MPC755 CBGA The package parameters are as provided in the following list. The package type is 25 × 25 mm, 360-lead ceramic ball grid array (CBGA). Package outline Interconnects Pitch Minimum module height ...
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Package Parameters for the MPC755 PBGA The package parameters are as provided in the following list. The package type is 25 × 25 mm, 360-lead plastic ball grid array (PBGA). Package outline Interconnects Pitch Minimum module height Maximum module ...
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System Design Information 8 System Design Information This section provides electrical and thermal design recommendations for successful application of the MPC755. 8.1 PLL Configuration The MPC755 PLL is configured by the PLL_CFG[0:3] signals. For a given SYSCLK (bus) frequency, the ...
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Table 16. MPC755 Microprocessor PLL Configuration Example for 400 MHz Parts (continued) Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz) PLL_CFG Bus-to- Core-to- [0:3] Core Multiplier Multiplier 0011 PLL off/bypass 1111 PLL off Notes: 1. PLL_CFG[0:3] settings not listed ...
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System Design Information Table 17. Sample Core-to-L2 Frequencies (continued) Core Frequency (MHz) 375 400 Note: The core and L2 frequencies are for reference only. Some examples may represent core or L2 frequencies which are not useful, not supported, or not ...
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These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0508 or 0603 orientations where connections are made along the length of the part. ...
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System Design Information Figure 22 describes the driver impedance measurement circuit described above. Figure 22. Driver Impedance Measurement Circuit Alternately, the following is another method to determine the output impedance of the MPC755. A voltage source connected ...
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Table 18 summarizes the signal impedance results. The driver impedance values were characterized at 0°, 65°, and 105°C. The impedance increases with junction temperature and is relatively unaffected by bus voltage. Impedance 8.6 Pull-Up Resistor Requirements The ...
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System Design Information should be left unconnected by the system. If all parity generation is disabled through HID0, then all parity checking should also be disabled through HID0, and all parity pins may be left unconnected by the system. The ...
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From Target Board Sources (if any Key 11 12 KEY 13 No Pin 15 16 COP Connector Physical Pin Out Notes: 1. RUN/STOP, normally found on pin 5 of ...
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System Design Information There is no standardized way to number the COP header shown in pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom, while still others number the ...
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The board designer can choose between several types of heat sinks to place on the MPC755. There are several commercially-available heat sinks for the MPC755 provided by the following vendors: Aavid Thermalloy 80 Commercial St. Concord, NH 03301 Internet: www.aavidthermalloy.com ...
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System Design Information External Resistance Internal Resistance External Resistance (Note the internal versus external package resistance.) Figure 26. C4 Package with Heat Sink Mounted to a Printed-Circuit Board 8.8.2 Adhesives and Thermal Interface Materials A thermal interface material is recommended ...
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Figure 27. Thermal Performance of Select Thermal Interface Materials The board designer can choose between several types of thermal interface. Heat sink adhesive materials should be selected based on high conductivity, yet adequate ...
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System Design Information Shin-Etsu MicroSi, Inc. 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com Thermagon Inc. 4707 Detroit Ave. Cleveland, OH 44102 Internet: www.thermagon.com 8.8.3 Heat Sink Selection Example This section provides a heat sink selection example using one ...
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Figure 28. Thermalloy #2328B Heat Sink-to-Ambient Thermal Resistance Versus Airflow Velocity Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-of-merit used for comparing the thermal performance ...
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Document Revision History 9 Document Revision History Table 19 provides a revision history for this hardware specification. Revision Date 8 2/8/2006 Changed processor descriptor from ‘B’ to ‘C’ for 350 MHz devices and increased power specifications for full-power mode in ...
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Table 19. Document Revision History (continued) Revision Date 4 — Added 450 MHz speed bin. Changed Table 16 to show 450 MHz part in example. Added row for 433 and 450 MHz core frequencies to Table 17. In Section 1.8.8, ...
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Document Revision History Table 19. Document Revision History (continued) Revision Date 1 — Corrected errors in Section 1.2. Removed references to MPC745 CBGA package in Sections 1.3 and 1.4. Added airflow values for Corrected V IH Power consumption values added ...
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Ordering Information Ordering information for the devices fully covered by this specification document is provided in Section 10.1, “Part Numbers Fully Addressed by This Document.” correspond to a maximum processor core frequency. For available frequencies, contact your local Freescale ...
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Ordering Information 10.2 Part Numbers Not Fully Addressed by This Document Devices not fully addressed in this document are described in separate hardware specification addendums which supplement and supersede this document, as described in the following tables. Table 21. Part ...
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Part Marking Parts are marked as the example shown in XPC745B PX350LE MMMMMM ATWLYYWWA Notes : MMMMMM is the 6-digit mask number. ATWLYYWWA is the traceability code. CCCCC is the country of assembly. This space is left blank if ...
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... Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. The described product contains a PowerPC processor core. The PowerPC name is a trademark of IBM Corp. and used under license. All other product or service names are the property of their respective owners. © ...