mpc755ed Freescale Semiconductor, Inc, mpc755ed Datasheet - Page 38

• Manufacturer Part Number: mpc755ed
• Description: Risc Microprocessor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

System Design Information
8.2
The AV
generation PLL and L2 cache DLL, respectively. To ensure stability of the internal clock, the power
supplied to the AV
frequency range of the PLL. A circuit similar to the one shown in
with minimum Effective Series Inductance (ESL) is recommended. Consistent with the recommendations
of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993),
multiple small capacitors of equal value are recommended over a single large value capacitor.
The circuit should be placed as close as possible to the AV
circuits. An identical but separate circuit should be placed as close as possible to the L2AV
often possible to route directly from the capacitors to the AV
BGA footprint, without the inductance of vias. The L2AV
proportionately less critical.
Figure 21
8.3
Due to the MPC755 dynamic power management feature, large address and data buses, and high operating
frequencies, the MPC755 can generate transient power surges and high frequency noise in its power
supply, especially while driving large capacitive loads. This noise must be prevented from reaching other
components in the MPC755 system, and the MPC755 itself requires a clean, tightly regulated source of
power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at
each V
capacitors receive their power from separate V
utilizing short traces to minimize inductance.
38
DD
DD
PLL Power Supply Filtering
Decoupling Recommendations
, OV
shows the PLL power supply filter circuit.
and L2AV
DD
Note: The core and L2 frequencies are for reference only. Some examples may
Core Frequency (MHz)
, and L2OV
DD
V
DD
represent core or L2 frequencies which are not useful, not supported, or not
tested for by the MPC755; see
valid L2CLK frequencies. The L2CR[L2SL] bit should be set for L2CLK
frequencies less than 110 MHz.
input signal should be filtered of any noise in the 500 kHz to 10 MHz resonant
DD
MPC755 RISC Microprocessor Hardware Specifications, Rev. 8
power signals are provided on the MPC755 to provide power to the clock
375
400
Table 17. Sample Core-to-L2 Frequencies (continued)
DD
Figure 21. PLL Power Supply Filter Circuit
10 Ω
pin of the MPC755. It is also recommended that these decoupling
2.2 µF
375
400
÷1
DD
Section 4.2.3, “L2 Clock AC Specifications,”
GND
, (L2)OV
÷1.5
250
266
Low ESL Surface Mount Capacitors
2.2 µF
DD
DD
DD
DD
pin may be more difficult to route, but is
pin to minimize noise coupled from nearby
, and GND power planes in the PCB,
188
200
÷2
Figure 21
pin, which is on the periphery of the 360
AV
DD
÷2.5
150
160
(or L2AV
using surface mount capacitors
DD
125
133
÷3
)
Freescale Semiconductor
for
DD
pin. It is