mpc755ed Freescale Semiconductor, Inc, mpc755ed Datasheet - Page 13

• Manufacturer Part Number: mpc755ed
• Description: Risc Microprocessor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

Figure 3
4.2.2
Table 9
Figure
Specifications.”
Freescale Semiconductor
Mode select input setup to HRESET
HRESET to mode select input hold
Notes:
1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input
2. The symbology used for timing specifications herein follows the pattern of t
3. The setup and hold time is with respect to the rising edge of HRESET (see
4. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a minimum of
5. t
6. Mode select signals are BVSEL, L2VSEL, PLL_CFG[0:3], and TLBISYNC.
7. Guaranteed by design and characterization.
8. Bus mode select pins must remain stable during operation. Changing the logic states of BVSEL or L2VSEL during operation
At recommended operating conditions (see
s
SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the signal
in question. All output timings assume a purely resistive 50-Ω load (see
the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
t
to the SYSCLK reference (K) going to the high (H) state or input setup time. And t
(K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can be read as the time that the input
signal (I) went invalid (X) with respect to the rising clock edge (KH)—note the position of the reference and its state for
inputs—and output hold time can be read as the time from the rising edge (KH) until the output went invalid (OX).
255 bus clocks after the PLL-relock time during the power-on reset sequence.
SYSCLK to compute the actual time duration (in ns) of the parameter in question.
will cause the bus mode voltage selection to change. Changing the logic states of the PLL_CFG pins during operation will
cause the PLL division ratio selection to change. Both of these conditions are considered outside the specification and are
not supported. Once HRESET is negated the states of the bus mode selection pins must remain stable.
(reference)(state)(signal)(state)
sysclk
6. Timing specifications for the L2 bus are provided in
is the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by the period of
provides the processor bus AC timing specifications for the MPC755 as defined in
provides the SYSCLK input timing diagram.
SYSCLK
Processor Bus AC Specifications
Table 9. Processor Bus Mode Selection AC Timing Specifications
Parameter
for outputs. For example, t
MPC755 RISC Microprocessor Hardware Specifications, Rev. 8
VM
Figure 3. SYSCLK Input Timing Diagram
t
Table
KHKL
t
SYSCLK
3)
VM = Midpoint Voltage (OV
VM
IVKH
symbolizes the time input signals (I) reach the valid state (V) relative
VM
Symbol
t
t
MVRH
MXRH
DD
Figure
Section 4.2.3, “L2 Clock AC
2
/2)
(signal)(state)(reference)(state)
Figure
5). Input and output timings are measured at
t
KR
All Speed Grades
Min
KHOV
8
0
4).
symbolizes the time from SYSCLK
Electrical and Thermal Characteristics
Max
—
—
1
for inputs and
t
t
KV
KV
KF
Unit
sysclk
ns
Figure 4
IH
IL
3, 4, 5,
3, 4, 6,
Notes
6, 7
7, 8
and
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