dp83846a National Semiconductor Corporation, dp83846a Datasheet - Page 48
dp83846a
Manufacturer Part Number
dp83846a
Description
Dsphyter ? Single 10/100 Ethernet Transceiver
Manufacturer
National Semiconductor Corporation
Datasheet
1.DP83846A.pdf
(59 pages)
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6.4.3 100BASE-TX Transmit Packet Latency Timing
Note: Latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of
TX_EN to the first bit of the “J” code group as output from the TD pins.
6.4.4 100BASE-TX Transmit Packet Deassertion Timing
Note: Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deasser-
tion of TX_EN to the first bit of the “T” code group as output from the TD pins.
T4.3.1
T4.4.1
Parameter
Parameter
TX_CLK to TD Latency
TX_CLK to TD Deassertion
TX_CLK
TX_CLK
TX_EN
TXD
TD
TX_EN
TXD
Description
Description
TD
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IDLE
DATA
DATA
T4.3.1
T4.4.1
48
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Notes
Notes
(T/R)
(J/K)
(T/R)
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IDLE
DATA
IDLE
Min
Min
Typ
Typ
Max
Max
6.0
www.national.com
6.0
bit times
bit times
Units
Units
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