dp83846a National Semiconductor Corporation, dp83846a Datasheet - Page 8

• Manufacturer Part Number: dp83846a
• Description: Dsphyter ? Single 10/100 Ethernet Transceiver
• Manufacturer: National Semiconductor Corporation

1.6 Strapping Options/Dual Purpose Pins
A 5 k resistor should be used for pull-down or pull-up to change the default strap option. If the default option is required,
then there is no need for external pull-up or pull down resistors, since the internal pull-up or pull down resistors will set
the default value. Please note that the PHYAD[0:4] pins have no internal pull-ups or pull-downs and they must be
strapped. Since these pins may have alternate functions after reset is deasserted, they should not be connected directly
to Vcc or GND.
LED_DPLX/PHYAD0
LED_COL/PHYAD1
LED_GDLNK/PHYAD2
LED_TX/PHYAD3
LED_RX/PHYAD4
AN_EN
AN_1
AN_0
Signal Name
S, O
S, O, PU
Type
33
32
31
30
29
27, 26, 25 Auto-Negotiation Enable: When high enables Auto-Nego-
Pin #
8
PHY ADDRESS [4:0]: The DP83846A provides five PHY
address pins, the state of which are latched into the PHYC-
TRL register at system Hardware-Reset.
The DP83846A supports PHY Address strapping values 0
(<00000>) through 31 (<11111>). PHY Address 0 puts
the part into the MII Isolate Mode. The MII isolate mode
must be selected by strapping Phy Address 0; changing to
Address 0 by register write will not put the Phy in the MII
isolate mode.
The status of these pins are latched into the PHY Control
Register during Hardware-Reset. (Please note these pins
have no internal pull-up or pull-down resistors and they must
be strapped high or low using 5 k resistors.)
tiation with the capability set by ANO and AN1 pins. When
low, puts the part into Forced Mode with the capability set
by AN0 and AN1 pins.
AN0 / AN1: These input pins control the forced or adver-
tised operating mode of the DP83846A according to the fol-
lowing table. The value on these pins is set by connecting
the input pins to GND (0) or V
These pins should NEVER be connected directly to
GND or V
The value set at this input is latched into the DP83846A at
Hardware-Reset.
The float/pull-down status of these pins are latched into the
Basic Mode Control Register and the Auto_Negotiation Ad-
vertisement Register during Hardware-Reset. After reset is
deasserted, these pins may switch to outputs so if pull-ups
or pull-downs are implemented, they should be pulled
through a 5k resistor.
The default is 111 since these pins have pull-ups.
AN_EN AN1
AN_EN AN1
0
0
0
0
1
1
1
1
CC.
0
0
1
1
0
0
1
1
AN0
AN0
0
1
0
1
0
1
0
1
Description
10BASE-T, Half-Duplex
10BASE-T, Full-Duplex
100BASE-TX, Half-Duplex
100BASE-TX, Full-Duplex
10BASE-T, Half/Full-Duplex
100BASE-TX, Half/Full-Duplex
10BASE-T Half-Duplex
100BASE-TX, Half-Duplex
10BASE-T, Half/Full-Duplex
100BASE-TX, Half/Full-Duplex
CC
(1) through 5 k resistors.
Advertised Mode
Forced Mode
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