adau1461 Analog Devices, Inc., adau1461 Datasheet - Page 37

• Manufacturer Part Number: adau1461
• Description: Sigmadsp Stereo, Low Power, 96 Khz, 24-bit Audio Codec With Integrated Pll Adau1461
• Manufacturer: Analog Devices, Inc.

The R/ W bit determines the direction of the data. A Logic 0 on
the LSB of the first byte means that the master will write infor-
mation to the peripheral, whereas a Logic 1 means that the
master will read information from the peripheral after writing
the subaddress and repeating the start address. A data transfer
takes place until a stop condition is encountered. A stop
condition occurs when SDA transitions from low to high while
SCL is held high.
and
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, the ADAU1461 immediately
jumps to the idle condition. During a given SCL high period,
(CONTINUED)
(CONTINUED)
(CONTINUED)
(CONTINUED)
START BY
Figure 50
(CONTINUED)
(CONTINUED)
MASTER
SDA
SCL
START BY
SDA
SCL
MASTER
SDA
SCL
SDA
SDA
SCL
SCL
shows an I
Figure 49
0
0
1
2
C read.
shows the timing of an I
1
1
SUBADDRESS BYTE 2
CHIP ADDRESS BYTE
READ DATA BYTE 1
1
1
CHIP ADDRESS BYTE
FRAME 1
FRAME 3
FRAME 5
SUBADDRESS BYTE 2
1
0
FRAME 1
FRAME 3
ADDR1
0
ADDR1
ADDR0
Figure 50. I
Figure 49. I
2
C write,
ADDR0
R/W
ADAU1461
ADAU1461
MASTER
2
ACK BY
ACK BY
C Read from ADAU1461 Clocking
2
Rev. 0 | Page 37 of 88
C Write to ADAU1461 Clocking
R/W
ACK BY
ADAU1461
ADAU1461
ACK BY
ACK BY
STOP BY
MASTER
REPEATED
START BY MASTER
the user should only issue one start condition, one stop condition,
or a single stop condition followed by a single start condition. If
an invalid subaddress is issued by the user, the ADAU1461 does
not issue an acknowledge and returns to the idle condition.
If the user exceeds the highest subaddress while in autoincrement
mode, one of two actions is taken. In read mode, the ADAU1461
outputs the highest subaddress register contents until the master
device issues a no acknowledge, indicating the end of a read. A
no acknowledge condition is where the SDA line is not pulled
low on the ninth clock pulse on SCL. If the highest subaddress
location is reached while in write mode, the data for the invalid
byte is not loaded into any subaddress register, a no acknowledge
is issued by the ADAU1461, and the part returns to the idle
condition.
0
SUBADDRESS BYTE 1
1
FRAME 2
CHIP ADDRESS BYTE
SUBADDRESS BYTE 1
DATA BYTE 1
1
FRAME 4
FRAME 4
FRAME 2
1
0
ADDR1
ADAU1461
ADDR0
ACK BY
ADAU1461
ADAU1461
ACK BY
ACK BY
R/W
ADAU1461
ACK BY
ADAU1461
STOP BY
MASTER