adau1461 Analog Devices, Inc., adau1461 Datasheet - Page 62

• Manufacturer Part Number: adau1461
• Description: Sigmadsp Stereo, Low Power, 96 Khz, 24-bit Audio Codec With Integrated Pll Adau1461
• Manufacturer: Analog Devices, Inc.

ADAU1461
R17: Converter Control 0, 16,407 (0x4017)
Bit 7
Reserved
Table 49. Converter Control 0 Register
Bits
[6:5]
4
3
[2:0]
R18: Converter Control 1, 16,408 (0x4018)
Bit 7
Table 50. Converter Control 1 Register
Bits
[1:0]
Bit Name
DAPAIR[1:0]
DAOSR
ADOSR
CONVSR[2:0]
Bit Name
ADPAIR[1:0]
Bit 6
Bit 6
Description
On-chip DAC serial data selection in TDM 4 or TDM 8 mode.
Setting
00
01
10
11
DAC oversampling ratio. This bit cannot be set for 64× when CONVSR[2:0] is set to 96 kHz.
0 = 128× (default).
1 = 64×.
ADC oversampling ratio. This bit cannot be set for 64× when CONVSR[2:0] is set to 96 kHz.
0 = 128× (default).
1 = 64×.
Converter sampling rate. The ADCs and DACs operate at the sampling rate set in this register. The converter rate
selected is a ratio of the base sampling rate, f
of the core clock.
Setting
000
001
010
011
100
101
110
111
Description
On-chip ADC serial data selection in TDM 4 or TDM 8 mode.
Setting
00
01
10
11
DAPAIR[1:0]
Bit 5
Bit 5
Reserved
Bit 4
DAOSR
Bit 4
Pair
First pair (default)
Second pair
Third pair
Fourth pair
Sampling Rate
f
f
f
f
f
f
f
Reserved
Pair
First pair (default)
Second pair
Third pair
Fourth pair
S
S
S
S
S
S
S
Rev. 0 | Page 62 of 88
/6
/4
/3
/2
/1.5
/0.5
Bit 3
ADOSR
Bit 3
S
. The base sampling rate is determined by the operating frequency
Bit 2
Bit 2
Base Sampling Rate (f
48 kHz, base (default)
8 kHz
12 kHz
16 kHz
24 kHz
32 kHz
96 kHz
Bit 1
Bit 1
CONVSR[2:0]
S
= 48 kHz)
ADPAIR[1:0]
Bit 0
Bit 0