lan9116 Standard Microsystems Corp., lan9116 Datasheet - Page 74

• Manufacturer Part Number: lan9116
• Description: Lan9116 Highly Efficient Single-chip 10/100 Non-pci Ethernet Controller
• Manufacturer: Standard Microsystems Corp.

Revision 1.5 (07-11-08)
5.3.5
5.3.6
31-24
23-16
BITS
BITS
31:0
15-8
7-0
DESCRIPTION
Byte Test
DESCRIPTION
TX Data Available Level. The value in this field sets the level, in number
of 64 Byte blocks, at which the TX FIFO Available interrupt (TFDA) will be
generated. When the TX data FIFO free space is greater than this value a
TX FIFO Available interrupt (TDFA) will be generated.
TX Status Level. The value in this field sets the level, in number of
DWORDs, at which the TX Status FIFO Level interrupt (TSFL) will be
generated. When the TX Status FIFO used space is greater than this value
an TX Status FIFO Level interrupt (TSFL) will be generated.
Reserved
RX Status Level. The value in this field sets the level, in number of
DWORDs, at which the RX Status FIFO Level interrupt (RSFL) will be
generated. When the RX Status FIFO used space is greater than this value
an RX Status FIFO Level interrupt (RSFL) will be generated.
BYTE_TEST—Byte Order Test Register
This register can be used to determine the byte ordering of the current configuration
FIFO_INT—FIFO Level Interrupts
This register configures the limits where the FIFO Controllers will generate system interrupts.
Offset:
Offset:
64h
68h
DATASHEET
74
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Size:
Size:
32 bits
32 bits
TYPE
TYPE
R/W
R/W
R/W
RO
RO
SMSC LAN9116
87654321h
DEFAULT
DEFAULT
48h
00h
00h
Datasheet
-