lan9500 Standard Microsystems Corp., lan9500 Datasheet - Page 14

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lan9500

Manufacturer Part Number
lan9500
Description
Lan9500/lan9500i Hi-speed Usb 2.0 To 10/100 Ethernet Controller
Manufacturer
Standard Microsystems Corp.
Datasheet

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Revision 1.4 (07-07-08)
NUM PINS
NUM PINS
1
1
1
1
1
Note 2.1
Note 2.2
(Internal PHY
Receive Data
Configuration
Power Select
Configuration
Chip Select
PHY Mode)
Auto-MDIX
Port Reset
JTAG Test
EEPROM
EEPROM
EEPROM
EEPROM
Data Out
(External
Data In
Enable
NAME
NAME
Mode)
Clock
Strap
Strap
0
Configuration strap values are latched on power-on reset and system reset. Configuration
straps are identified by an underlined symbol name. Signals that function as configuration
straps must be augmented with an external resistor when connected to a load.
Configuration strap values are latched on power-on reset and system reset. Configuration
straps are identified by an underlined symbol name. Signals that function as configuration
straps must be augmented with an external resistor when connected to a load.
AUTOMDIX_EN
PWR_SEL
SYMBOL
SYMBOL
EECLK
nTRST
EEDO
EECS
RXD0
EEDI
Table 2.2 EEPROM Pins
Table 2.3 JTAG Pins
DATASHEET
BUFFER
BUFFER
TYPE
TYPE
(PD)
(PU)
(PU)
(PD)
(PD)
(PU)
(PD)
O8
O8
O8
IS
IS
IS
IS
IS
14
EEPROM Data In: This pin is driven by the
EEDO output of the external EEPROM.
EEPROM Data Out: This pin drives the EEDI
input of the external EEPROM.
Auto-MDIX Enable Configuration Strap:
Determines the default Auto-MDIX setting.
0 = Auto-MDIX is disabled.
1 = Auto-MDIX is enabled.
See
configuration straps.
EEPROM chip select: This pin drives the chip
select output of the external EEPROM.
EEPROM Clock: This pin drives the EEPROM
clock of the external EEPROM.
Power Select Configuration Strap: Determines
the default power setting when no EEPROM is
present.
0 = The LAN9500/LAN9500i is bus powered.
1 = The LAN9500/LAN9500i is self powered.
See
configuration straps.
JTAG Test Port Reset (Active-Low): In internal
PHY mode, this pin functions as the JTAG test
port reset input.
Receive Data 0: In external PHY mode, this pin
functions as the receive data 0 input from the
external PHY.
Note 2.2
Note 2.2
Hi-Speed USB 2.0 to 10/100 Ethernet Controller
for more information on
for more information on
DESCRIPTION
DESCRIPTION
SMSC LAN9500/LAN9500i
Datasheet

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