peb20550 Infineon Technologies Corporation, peb20550 Datasheet - Page 118

• Manufacturer Part Number: peb20550
• Description: Extended Pcm Interface Controller
• Manufacturer: Infineon Technologies Corporation

CFI Bit Timing and Bit Shift CMD2, CTAR, CBSR
The position of the CFI frame can be shifted relative to the CFI frame synchronization
pulse using the CFI Time slot Adjustment Register CTAR and the CFI Bit Shift Register
CBSR. This shifting can be performed simultaneously for up- and downstream directions
with a one bit resolution by up to a whole frame. The upstream frame can additionally be
shifted relative to the downstream frame by up to 15 bits. Furthermore, the polarity of the
clock edge (CRCL) used for transmitting and sampling the data can be programmed in
the CMD2 register.
Since the frame synchronization source of the configurable interface is either PFS (for
CMD1:CSS = 0) or FSC (for CMD1:CSS = 1), the bit shift also refers to either the PFS
or the FSC framing signal.
Note: If PFS/PDC is selected as CFI sync/clock source, the time slot and bit shift
If FSC/DCL is selected as CFI sync/clock source, the time slot and bit shift functions
affect the CFI frame with respect to the FSC framing input signal. In this case, the CFI
frame start can be selected completely independently from the PCM frame start, it must
only be assured that a phase relationship once established between the CFI and PCM
frames is maintained all the time.
Semiconductor Group
values programmed to CTAR and CBSR:CDS2 … 0 affect both the CFI data lines
and the CFI output framing signal FSC. The CFI frame together with the FSC
signal can thus be shifted with respect to the PCM frame (PFS). The position of
the CFI frame relative to the FSC output signal is not affected by these settings
but is instead determined by the FSC framing control mode programmed to
CMD2:FC2 … 0. The upstream CFI frame can, however, still be shifted relative to
the downstream CFI frame with the CBSR:CUS3 … 0 bits.
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Application Hints
PEB 2055
PEF 2055