peb20550 Infineon Technologies Corporation, peb20550 Datasheet - Page 45

• Manufacturer Part Number: peb20550
• Description: Extended Pcm Interface Controller
• Manufacturer: Infineon Technologies Corporation

3.5.2.4 Initialization of the Upstream Data Memory (DM) Tristate Field
For each PCM time slot the tristate field defines whether the contents of the DM data
field are to be transmitted (low impedance), or whether the PCM time slot shall be set to
high impedance. The contents of the tristate field is not modified by a hardware reset. In
order to have all PCM time slots set to high impedance upon the activation of the PCM-
interface, each location of the tristate field must be loaded with the value ’0000’. For this
purpose, the ‘tristate reset’ command can be used:
The initialization of the complete tristate field takes 1035 RCL cycles.
Note: It is also possible to program the value “0000” to the tristate field in order to have
Note: While OMDR:PSB = 0, all PCM-output drivers are set to high impedance,
3.5.3
With the EPIC configured to the system requirements, the PCM and CFI interface can
be switched to the operational mode.
The OMDR:OMS1..0 bits must be set (if this has not already be done) to the normal
operation mode (OMS1..0 = 11). When doing this, the PCM framing interrupt (ISTA:PFI)
will be enabled. If the applied clock and framing signals are in accordance with the
values programmed to the PCM-registers, the PFI interrupt will be generated (if not
masked). When reading the status register, the STAR:PSS-bit will be set to logical 1.
To enable the PCM-output drivers set OMDR:PSB = 1. The CFI interface is activated by
programming OMDR:CSB = 1. This enables the output clock and framing signals (DCL
and FSC), if these have been programmed as outputs. It also enables the CFI output
drivers. The output driver type can be selected between “open drain” and “tristate” with
the OMDR:COS bit.
Example: Activation of the EPIC for a typical IOM-2 application:
OMDR = EE
Semiconductor Group
all time slots switched to low impedance upon the activation of the PCM interface.
regardless of the values written to the tristate field.
OMDR =
MADR =
MACR =
Wait for STAR:MAC = 0
Activation of the PCM and CFI Interfaces
H
;
Normal operation mode (OMS1..0 = 11)
PCM interface active (PSB = 1)
PCM test loop disabled (PTL = 0)
CFI output drivers: open drain (COS = 1)
Monitor handshake protocol selected (MFPS = 1)
CFI active (CSB = 1)
Access to EPIC registers via address pins A3..A0, used in
demultiplexed mode only, normal operation (RBS = 0)
C0
00
68
H
H
H
; OMS1..0 = 11, normal mode
; code field value“0000”
; MOC-code to initialize all tristate locations (1101
45
B
Operational Description
PEB 2055
PEF 2055
B
)