peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 186

• Manufacturer Part Number: peb2256
• Description: E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
• Manufacturer: Infineon Technologies Corporation

5.6.6
Alarm simulation does not affect the normal operation of the device, i.e. all time slots
remain available for transmission. However, possible real alarm conditions are not
reported to the processor or to the remote end when the device is in the alarm simulation
mode.
The alarm simulation is initiated by setting the bit FMR0.SIM. The following alarms are
simulated:
• Loss-Of-Signal (LOS, red alarm)
• Alarm indication signal (AIS, blue alarm)
• Loss of pulse frame
• Remote alarm (yellow alarm) indication
• Receive and transmit slip indication
• Framing error counter
• Code violation counter
• CRC6 error counter
Some of the above indications are only simulated if the FALC56 is configured in a mode
where the alarm is applicable.
The alarm simulation is controlled by the value of the alarm simulation counter:
FRS2.ESC which is incremented by setting bit FMR0.SIM.
Clearing of alarm indications:
• Automatically for LOS, remote (yellow) alarm, AIS, and loss of synchronization and
• User controlled for slips by reading the corresponding interrupt status register ISR3.
• Error counter have to be cleared by reading the corresponding counter registers.
is only possible at defined counter steps of FRS2.ESC. For complete simulation
(FRS2.ESC = 0), eight simulation steps are necessary.
5.6.7
Single bit defects can be inserted into the transmit data stream for the following
functions:
FAS defect, multiframe defect, CRC defect, CAS defect, PRBS defect and bipolar
violation.
Defect insertion is controlled by register IERR.
Data Sheet
Alarm Simulation (T1/J1)
Single Bit Defect Insertion
186
Functional Description T1/J1
FALC56 V1.2
PEB 2256
2002-08-27