peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 264
peb2256
Manufacturer Part Number
peb2256
Description
E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEB2256.pdf
(490 pages)
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If access to these registers is done without control of the interrupt ISR1.XMB the
registers should be written twice to avoid an internal data transfer error.
Note: A software reset (CMDR.XRES) resets these registers.
Port Configuration 1 to 4 (Read/Write)
Value after reset: 00
PC1
PC2
PC3
PC4
RPC(2:0)
Data Sheet
7
RPC12
RPC22
RPC32
RPC42
Receive multifunction port configuration
The multifunction ports RP(A to D) are bidirectional. After Reset these
ports are configured as inputs. With the selection of the pin function
the In/Output configuration is also achieved. The input function SYPR
may only be selected once, it must not be selected twice or more.
Register PC1 configures port RPA, while PC2 → port RPB,
PC3 → port RPC and PC4 → port RPD.
000 = SYPR: Synchronous Pulse Receive (Input)
001 = RFM: Receive Frame Marker (Output)
H
Together with register RC(1:0) SYPR defines the frame begin
on the receive system interface. Because of the offset
programming the SYPR and the RFM pin function cannot be
selected in parallel.
CMR2.IRSP = 0:
The receive frame marker is active high for one 2.048 MHz
period during any bit position of the current frame.
Programming of the bit position is done by using registers
RC(1:0). The internal time slot assigner is disabled. The RFM
offset calculation formula has to be used.
CMR2.IRSP = 1:
Internally generated frame synchronization pulse sourced by
the DCO-R circuitry. The pulse is active low for one 2.048 MHz
period.
RPC11
RPC21
RPC31
RPC41
RPC10
RPC20
RPC30
RPC40
264
XPC13
XPC23
XPC33
XPC43
XPC12
XPC22
XPC32
XPC42
XPC11
XPC21
XPC31
XPC41
XPC10
XPC20
XPC30
XPC40
FALC56 V1.2
E1 Registers
0
PEB 2256
2002-08-27
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