peb2256 Infineon Technologies Corporation, peb2256 Datasheet - Page 431
peb2256
Manufacturer Part Number
peb2256
Description
E1/t1/j1 Framer And Line Interface Component For Long And Short Haul Applications
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEB2256.pdf
(490 pages)
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SUEX
XLSC
XPR
Interrupt Status Register 2 (Read)
ISR2
All bits are reset when ISR2 is read.
If bit GCR.VIS is set, interrupt statuses in ISR2 are flagged although they are masked by
register IMR2. However, these masked interrupt statuses neither generate a signal on
INT, nor are visible in register GIS.
FAR
Data Sheet
FAR
7
Transmit Multiframe Begin
This bit is set with the beginning of a transmitted multiframe related to
the internal transmit line interface timing.
Signaling Unit Error Threshold Exceeded - HDLC Channel 1
Masks the indication by interrupt that the selected error threshold for
SS7 signaling units has been exceeded.
0 =
1 =
Note: SUEX is only valid, if SS7 mode is selected.
Transmit Line Status Change
XLSC is set with the rising edge of the bit FRS1.XLO or with any
change of bit FRS1.XLS.
The actual status of the transmit line monitor can be read from the
FRS1.XLS and FRS1.XLO.
Transmit Pool Ready - HDLC Channel 1
A data block of up to 32 bytes can be written to the transmit FIFO.
XPR enables the fastest access to XFIFO. It has to be used for
transmission of long frames, back-to-back frames or frames with
shared flags.
Frame Alignment Recovery
The framer has reached synchronization. Set with the falling edge of
bit FRS0.LFA.
It is set also after alarm simulation is finished and the receiver is still
synchronous.
LFA
Signaling unit error count below selected threshold
Signaling unit error count exceeded selected threshold
If SUEX is caused by an aborted/invalid frame, the interrupt
will be issued regularly until a valid frame is received (e.g. a
FISU).
MFAR
LMFA
431
AIS
LOS
RAR
T1/J1 Registers
FALC56 V1.2
RA
0
PEB 2256
2002-08-27
(6A)
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