lpc47s457-ns Standard Microsystems Corp., lpc47s457-ns Datasheet - Page 123

• Manufacturer Part Number: lpc47s457-ns
• Description: Advanced I/o With X-bus Interface
• Manufacturer: Standard Microsystems Corp.

6.14 Power On Elapsed Timer (POET)
The LPC47S45x is equipped with two counters to monitor the length of time VCC and VTR are active. Each counter
clocks one second per LSBit. The one second clock input to the counter is derived from the 32.768 KHz clock
input(i.e. CLKI32). This input is powered by VCC and maintained by VTR when VCC is removed. The counter
values are maintained in the Runtime Register section and are accessible by either the LPC Bus or SMBus. When
the value is read from the register, all 32 bits are latched to avoid the value being updated during a read. Latching of
these bytes will not effect the continued counting of the counter. The only time the counter is reset is on a Vbat POR
or when the counter reaches its’ maximum value of FFFFFFFFh, It is unlikely that the counter will ever reach its’
maximum, since it would take in excess of 136 years for the 32 bit counter to reach its’ maximum.
These counters may be accessed by the LPC bus through the Runtime Registers at offsets 6Dh to 74h or by the
SMBus in the SMBus2 Registers at offsets 04h to 0Bh. Since the counters are read-only, no arbitration is necessary
between the LPC Bus and the SMBus. See Table 60 − Runtime Register Block Summary – Power On Elapsed Time
Counters. The counter registers will map into the SMBus 8-bit registers address field for SMBus Read access as
described in section 6.18.4 SMBus2 Register Summary on page 139.
6.14.1 VCC POWER ON ELAPSED TIME COUNTER
In the Runtime Register Block, at offsets 6Dh through 70h, a 4 byte counter is used to indicate power on elapsed time
for Vcc. The counter is powered by VCC and is enabled by Vcc PWRGD. It should be noted that the counter value is
maintain by Vbat and therefore may only be reset by Vbat POR as shown in Table 60. When Byte 1 (LSB) is read, by
the LPC Bus or SMBus, Bytes 2 through 4 are latched for eventual read. It is required the counter (Bytes 1 through 4)
be read LSB to MSB. Latching of bytes for read output will not affect continued counting.
6.14.2 VTR POWER ON ELAPSED TIME COUNTER
In the Runtime Register Block, at offsets 71h through 74h, a 4 byte counter is used to indicate power on elapsed time
for Vtr. The counter is powered by Vtr and is enabled by Vtr PWRGD as shown in Table 60. When Byte 1 (LSB) is
read, by the LPC Bus or SMBus, Bytes 2 through 4 are latched for eventual read. It is required the counter (Bytes 1
through 4) be read LSB to MSB. Latching of bytes for read output will not affect continued counting.
SMSC LPC47S45x
(HEX)
OFFS
ET
6D
6E
6F
70
71
72
73
74
TYPE
R
R
R
R
R
R
R
R
Table 60 − Runtime Register Block Summary – Power On Elapsed Time Counters
RESET
PCI
-
-
-
-
-
-
-
-
VCC
POR
-
-
-
-
-
-
-
-
POR
VTR
-
-
-
-
-
-
-
-
DATASHEET
VBAT
0X00
0X00
0X00
0X00
0X00
0X00
0X00
0X00
POR
Page 123 of 259
RESET
SOFT
-
-
-
-
-
-
-
-
Vcc_CNT4 Byte 4 (MSB)
Vcc_CNT1 Byte 1 (LSB)
Vtr_CNT4 Byte 4 (MSB)
Vtr_CNT1 Byte 1 (LSB)
Vcc_CNT2 Byte 2
Vcc_CNT3 Byte 3
Vtr_CNT2 Byte 2
Vtr_CNT3 Byte 3
REGISTER
SMBUS2
OFFSET
REG
0A
0B
04
05
06
07
08
09
Rev. 08-10-09