lpc47s457-ns Standard Microsystems Corp., lpc47s457-ns Datasheet - Page 95

• Manufacturer Part Number: lpc47s457-ns
• Description: Advanced I/o With X-bus Interface
• Manufacturer: Standard Microsystems Corp.

Table 42 illustrates the AT and PS/2 (including Model 30) configuration registers available and the type of access
permitted. In order to maintain software transparency, access to all the registers must be maintained. As Table 42
shows, two sets of registers are distinguished based on whether their access results in the part remaining in powerdown
state or exiting it.
Access to all other registers is possible without awakening the part.
powerdown without changing the status of the part. A read from these registers will reflect the true status as shown in
the register description in the FDC description. A write to the part will result in the part retaining the data and
subsequently reflecting it when the part awakens. Accessing the part during powerdown may cause an increase in the
power consumption by the part. The part will revert back to its low power mode when the access has been completed.
Pin Behavior
The LPC47S45x is specifically designed for systems in which power conservation is a primary concern. This makes the
behavior of the pins during powerdown very important.
The pins of the LPC47S45x can be divided into two major categories: system interface and floppy disk drive interface.
The floppy disk drive pins are disabled so that no power will be drawn through the part as a result of any voltage applied
to the pin within the part's power supply range. Most of the system interface pins are left active to monitor system
accesses that may wake up the part.
Note 1: Writing to the DOR or DSR does not wake up the part, however, writing any of the motor enable
bits or doing a software reset (via DOR or DSR reset bits) will wake up the part.
System Interface Pins
Table 43 gives the state of the interface pins in the powerdown state. Pins unaffected by the powerdown are labeled
"Unchanged".
FDD Interface Pins
SMSC DS – LPC47S45x
BASE + ADDRESS
00H
01H
02H
03H
04H
06H
07H
07H
04H
05H
SYSTEM PINS
Table 43 − State of System Pins in Auto Powerdown
PCI_RESET#
Access to these registers DOES NOT wake up the part
LFRAME#
SER_IRQ
PCI_CLK
Table 42 − PC/AT and PS/2 Available Registers
LAD[3:0]
LPCPD#
LDRQ#
Access to these registers wakes up the part
DOR (1)
DSR (1)
PC-AT
MSR
CCR
Data
AVAILABLE REGISTERS
DIR
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DATASHEET
Page 95 of 259
PS/2 (MODEL 30)
DOR (1)
DSR (1)
MSR
STATE IN AUTO POWERDOWN
CCR
Data
SRA
SRB
DIR
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---
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged
These registers can be accessed during
ACCESS PERMITTED
R/W
R/W
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W
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W
R
R
R
R
Rev. 04-30-07