xccace-tq144 Xilinx Corp., xccace-tq144 Datasheet - Page 19

• Manufacturer Part Number: xccace-tq144
• Description: Ic Ace Controller Chip Tq144
• Manufacturer: Xilinx Corp.

Interrupt Timing
The interrupt request and clearing cycles are shown in
Figure
HIGH) occurs sometime before Cycle 0. The interrupt
request is cleared by performing a single MPU write cycle
that sets RESETIRQ = 1 (bit number 11) in the CONTROL-
REG(15:0) register (BYTE address 0x19 or WORD address
0x0C).
DS080 (v2.0) October 1, 2008
Product Specification
15. In
R
Figure
CYCLE
CLK
MPA
MPD
MPCE
MPWE
MPOE
MPIRQ
15, the interrupt request (MPIRQ =
0ns
tDIRQ
Figure 15: Interrupt Request Timing
50ns
CONTROLREG(15:0) ADDRESS
www.xilinx.com
Cycle 0
tSOE
tSCE
tSA
The MPU interrupt request line (MPIRQ) remains active
HIGH until the RESETIRQ bit is set. The MPIRQ line
becomes inactive LOW two cycles after the completion of
the RESETIRQ write cycle (Cycle 4). For subsequent MPU
interrupt requests to be enabled, the RESETIRQ bit must be
reset and one of the three IRQ enable bits (DATABU-
FRDYIRQ, ERRORIRQ, and/or CFGDONEIRQ) in the
CONTROLREG register should be set.
Cycle 1
100ns
tSWE
tSD
0800h
tH
tH
tH
tH
Cycle 2
tH
tSWE
System ACE CompactFlash Solution
150ns
tH
Cycle 3
DS080_44_030501
tDIRQ
Cycle 4
19