sab82526n Infineon Technologies Corporation, sab82526n Datasheet - Page 47

• Manufacturer Part Number: sab82526n
• Description: High-level Serial Data Communications Ics
• Manufacturer: Infineon Technologies Corporation

4.5 FIFO Structure
In both transmit and receive direction 64-byte deep FIFO’s are provided for the intermediate
storage of data between the serial interface and the CPU interface. The FIFO’s are divided into
two halves of 32-bytes, where only one half is accessible to the CPU or DMA controller at any
time.
The organization of the Receive FIFO (RFIFO) is such, that in the case of a frame at most 64
bytes long, the whole frame may be stored in the RFIFO. After the first 32 bytes have been
received, the HSCX prompts to read the 32-byte block by means of interrupt or DMA request
(RPF interrupt or activation of DRQR line). This block remains in the RFIFO until a confirmation
is given to the HSCX acknowledging the transfer of the data block. This confirmation is either
a RMC (Receive Message Complete) command via the CMDR register in Interrupt Mode, or
is implicitly achieved in DMA mode after 32-bytes have been read from the RFIFO. As a result,
it’s possible in Interrupt Mode, to read out the data block any number of times until the RMC
command is issued.
The configuration of the RFIFO prior to and after acknowledgement is shown in figure 21.
Figure 21
Configuration of RFIFO (Long Frames)
Semiconductor Group
32
Inaccessible
32
Accessible
Bytes
Bytes
a) Prior to
Acknowledgement
Block
Block
B + 1
B
47
b) After
Acknowledgement
Block
B + 1
Free
ITD01582
SAB 82525
SAB 82526
SAF 82525
SAF 82526